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Negative hold time - is it possible and what does it mean?

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magicball

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Negative hold time

I found in my 0.18 ASIC standard cell library, the hold time of FFs is negative, about -0.2ns.

Is it possible? What does this mean?

Thanks
 

RTL2GDSII

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That means data can change before clock edge and no metastable will happen.
 

magicball

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RTL2GDSII, theoreticly, it is right. But I just cannot image the input data can be invalid before the clock edge and the output is still valid.
Can you explain it in more detail? When & why it can happen?

Thanks a lot!
 

shell3

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It basically mean that the propagation delay through the gates and wirings used to build the FF are such that the data may change 200ps before the clock edge and still meet the hold time requirement.
 

yeewang

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yes, it's true

hey, you can just imagine that the clock is delayed inside the FF......
 

yeewang

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yes, it's true

hey, you can just imagine that the clock is delayed inside the FF...... :lol:
 

always@smart

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as long as it's still in 10% of your constraint.Furturemore,it can be fixed in post-layout level
 

steak

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I think there's a more important reason than just an internal load for the clock greater than the data signal, as precised in the previous replies.

The hold time depends of the measure parameters. Usually, the hold time is specified from the 90% of the CLK rising edge to the 90% of a input falling edge (or 10% of a input rising edge). We assume the transition is taken at 50% of the edge.

So, draw a little picture of the signals and you will see that the hold time could be negative AND the effective transition (at 50%) of the clock is before the transition of the data, depending of the transition time (10%-90%) of the signals.

Best regards
 

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