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RTL2GDSII, theoreticly, it is right. But I just cannot image the input data can be invalid before the clock edge and the output is still valid.
Can you explain it in more detail? When & why it can happen?
I think there's a more important reason than just an internal load for the clock greater than the data signal, as precised in the previous replies.
The hold time depends of the measure parameters. Usually, the hold time is specified from the 90% of the CLK rising edge to the 90% of a input falling edge (or 10% of a input rising edge). We assume the transition is taken at 50% of the edge.
So, draw a little picture of the signals and you will see that the hold time could be negative AND the effective transition (at 50%) of the clock is before the transition of the data, depending of the transition time (10%-90%) of the signals.