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negative edge trigerring vs positive edge trigerring

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Full Member level 5
Feb 11, 2006
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positive edge negative

hi...,why is negative edge triggering more power saving than positive edge triggering... i came across that it is mainly because -ve edge triggering only does discharging operation while the +ve edge triggering charges the capacitance....could some one explain what are the transistors that are involved in this charging and dischaging... and why these operations take place...

positive edge negative edge

Can you show the particular circuit which saves more power on negative edge triggering FlipFlop?
As far as I know, there should be no difference regarding to positive/negative triggering F.F.

negative and positive edge detector

hi lordsathish,as far as i know,for the inverter,when the input is low level,PMOS is on and NMOS is off
the power is 1/2fCV^2
when input is high : PMOS is off and NMOS is on
the power is also 1/2fCV^2
in one clock cycle ,the total power is fCV^2
can you give me an example which saves power on negative edge triggering FF.
BR. varkylin

positive edge triggered, negative edge

Hi all,
You're right lordsathish concerning the power. Another point to note is that, in practice, the negative edge is harder to detect than the positive edge and require in certain cases additional circuitry. That's why positive triggering still better.

negative positive edge

negative triggering will trigger a ptype devive and hence less consume less power. But i am not clear why positive triggering is better? Masterpiece could you please elaborate?

positive edge vs negative edge

Pls elaborate more on this topic.
For me both are same. Pls state the examples from which you people drawing the conclusion

negative and positive edge triggered

there is no significant difference i believe ! anyways i hav to check !

why positive edge vs negative edge trigger

Hi all,
can any one tell why posedge flop are mostly used in designs...

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