Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] negation operator on inout-type signals

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
Code:
inout b,c;
assign c = ~b;


In the code above, doing such assign will result in XXX unknown situation which I presume is due to conflicting drivers ?
However, assign c = b; does not result in XXX unknown situation though. Why ?

I tried to use not a1(c, b); , but I think the simple not primitive gate does not support inout type

Any suggestions or comments ?

Code:
vcs.log:44:Error-[IGOE] Illegal gate output expression
vcs.log-45-TB.v, 49
vcs.log-46-  The following expression is illegally connected to gate.
vcs.log-47-  Expression: c
vcs.log-48-  Source info: not a1(c, b);
vcs.log-49- The gate connection must be a scalar net or bit-select of vector net.
 

Here are few things to remember to model inout ports:
  1. You can't read and write inout port simultaneously, hence kept highZ for reading.
  2. inout port can NEVER be of type reg.
  3. There should be a condition at which it should be written. (data in mem should be written when Write = 1 and should be able to read when Write = 0).
Before modeling an inout using HDL, think of how it looks in hardware.

1637054137006.png


I am not giving you direct answers, but if you think about these they should answer your question.
 

Your reply above concerns for 1 inout port.

I am actually trying to put a NOT gate in between 2 inout ports
--- Updated ---

I am not sure how tranif0 would help ?
 

I am actually trying to put a NOT gate in between 2 inout ports
It cannot be done in the way you are doing it.

In real life, if you look to the left hand side of the picture I have posted, an inout port is a physical pin on the chip!
If you look to the right hand side, you have in, out, oe signals to be used in RTL logic.

Only ports can be of inout type. Are you trying to do something in the testbench?

I am not sure how tranif0 would help ?
I have never used it, I do not know!
 
Last edited:

an inout port is a physical pin on the chip!
I am actually simulating coding for two devices, hence two inout ports as you saw in the first post.
 

thanks for the info. By the way, the issue is solved by modifying the internal input and output paths of the inout port
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top