a neg edge latch becomes transparent when the clock is low and you generally want the input data to settle before the latch becomes transparent(unless you allow the time borrowing). This makes the setup analysis to be done on falling edge of the clock.
A flop has the same neg edge latch as a master latch, but the path to a slave latch is closed when clock is low, so that even though the input data changes when clock is low, the data doens't propagate to the output pin of the flop. It means that the input data needs to settle before the path from the master to slave latch open up, which is when the clock goes high. So, the setup check is performed on rising edge.