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needs help on a LDO design problem

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morix

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Hi,

I had some difficulties designing a LDO with the following spec:

supply voltage 1.2V
output voltage 1V
output current range 10uA ~ 100uA
layout area must be small (large size resistors cannot be used)
other specs r kinda minor

the structure is a smple LDO consisting one PMOS power MOS, 2 resistors and an op-amp.

The problem I encountered is that since the desired output voltage is 1V and the output current is in ~uA. Therefore, the resistance must be in ~Mohm scale, which must be large in layout. So i'm looking for some thing to replace large resistors or some modification on LDO structure to resolve this problem.

I have tried to replace large resistors with diode-connected loads (PMOS), but there will be other problems, for example, the diode-connected load that is connected between output and op-amp, its resistance will vary when the output loading changes. Thus, we can't come up with a stable output voltage at 1V.

Can anyone give me some help here?
 

transbrother

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Unfortunately, in order to get a good LDO with good matching, performance, it is recommended that you use resistors for feedback.

If you tradeoff and burn about 5uA in the resistor string, you get about 200kOhms with 1V output. You can try to see if you can make additional tradeoff matching by using some very high sheet ro resistors such as nwell res., or similar ones.

If you use a diode connected device instead of resistors, your output voltage will not be able to move freely under slewing conditions as a diode connected device will give rise to low impedance node and will clamp the output voltage.
 

caosl

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If diode connected mos can solve the problem, there are many people do in this way. you can use external res to regulate the output coltage if resistor's area is the most factor which restrict your design.
 

ee_cchac

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mu.....i am fresh in LDO, but have some question would like to ask :

1>the uspply voltage is 1.2V....how about the reference voltage ?
2>the Vo is 1V, so thus the Power PMOS (PPMOS) size...will...


By the way, how about adding a voltage buffer between AMP and PPMOS ?
And is frequency compensation using ?
Is is possible to add more supply current ?
Also, it seems it is necesary to pay attention when loading @ lowest and largeest..the gain.......may.....not that happy...to you.

sorry that i indeed did not give any +ve suggestion......
 

morix

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external res and large passive res might not be feasible in my case. Becoz the ultimate goal of this chip is to implant into human body. That's why no large passive res and no external component can be used.


I set the reference voltage to be around 0.5V.
the freq compensation is done at the output of the OP and the output of LDO.
 

arghpok

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Those are the correct requirements of output current ?

It just seems like quiescent current. And if in fact you're needing such a low output current, the parasitic pole will be a pain in the ass for you if you want to implement this ldo without ext-cap.

About the resistors. mmm, have you checked other feedback topologies ? I would keep those resistors on chip, integrating them with highres poly, and if you won't count with this layer, diffussion layer with finer layout techniques will help you to minimize the area. You can make a very good capfree ldo with a 500x500 um layout area.
 

paley

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you can create a 1V voltage reference and it's very easy
 

arghpok

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It is different since the voltage references are not designed to give any current to any circuit (they're just to be connected to ttor's gates). I repeat, check for your specifications and then post a reply. I'm sure that is not the required output current.
 

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