Nice article.
At section II/A: Two poles at the gate? The dominant and the mirror pole? Mirror pole is not at the gate of MP I think. You didn't mention RHPZ, but not too hard to compensate that.
At section II/B: NMOS can be a native device without threshold voltage, so the max Vout can be higher. I know sometimes it is extra cost, but at 130nm probably not too big, I don't know.
PSRR is Power Supply Rejection. If it is negative that means the rejection is negative and the gain of supply noise is positive, but lot of engineer use negative value for it.
Did you run PVT and Monte Carlo? How much is the offset and Phase Margin variation? I am just curious, probably these are not the main things in a scientific article.