Need VHDL code for Residue to Binary Converter

[seneda]

Hai all,

Can anyone send the VHDL code for Residue to binary converter for the moduli set {2n-1, 2n, 2n+1}? Please i am expecting some one of u will help me.

Thank you,

 

[std_match]

Do you want a synthesizeable solution?
Do you want a combinatorial solution?

A combinatorial solution is probably very simple to write with the "mod" operator, but you can get into trouble if you want to synthesize it.
The synthesized logic will be slow and a lot of resources will be consumed if you want to handle large numbers. With too large numbers the logic will not fit in your hardware.

A state machine solution is a little more complicated to write and it will need several clock cycles to complete, but it is easy to synthesize, it consumes very little resources and it can handle numbers of any (practical) size.

 

[seneda]

I need both of them(synthesizeable solution and combinatorial solution), kindly send it. Those will be more useful for me.

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Actually i am going to design a fpga of residue to binary converter for the moduli set {2n+1, 2n, 2n-1}. Please help me. i need the VHDL code to proceed.
thank you.

 

[std_match]

Is this a school project?

I hope I don't misunderstand what you mean by "Residue to binary converter".
You want to calculate the remainder of x/y, where y is 2n+1, 2n or 2n-1,
and output the result as a binary number?

What is the range of 'x'?
What is 'n'? Range? A constant?

Some hints:
Use library "numeric_std", type "unsigned" or "signed" and operator "mod" or "rem".
Do a generic modulo block and switch between the denominators.
I don't think you can gain anything even if the set of denominators is very limited.

This will not require many lines of VHDL code, but it is possible that you will have some synthesis problems.
Post your code here if you have problems!

 

[seneda]

Hai i am doing my ME. i asked help for my ME project. I attached my base paper with this one. I need the VHDL Code for that Base Paper.

 

[std_match]

It seems that you want exactly the opposite of what I assumed. You have the remainders and want to calculate the dividend (numerator).
That is complicated, but it seems that you have a solution in your paper. You need someone to code your solution in VHDL.
It should be rather straightforward, but it probably takes more time than I can spend on this.
Your paper indicates that you have already implemented the solution in an FPGA. Was that in Verilog?

 

[seneda]

The code must be in VHDL.I have started my project recently, till now i was trying to simplify the theorem in order to achieve the simplified equation as in the paper. I have to proceed the VHDL for the hardware implementation in FPGA. can u help to build the code? because i dont know the VHDL language.