need verilog code for this circuit

[reachmagi]

hi all,

can anyone of you give a verilog code for this...

 

[lostinxlation]

Show me your code and I'll help you.

That circuit doesn't work well, though.

 

[reachmagi]

lostinxlation ,

according to the circuit, a connection should exist between q output and d input. however i try, couldnt come up with a code that will synthesize.

following is a code for the circuit, except that the connection btw q and d of FF is not coded..

can you please tell me how do i make connection so that the synthesized code will give the circuit given in image

module asg1(d, clk, a, out1);

input d, a, clk;
reg q;

output out1;
reg out1;


always@(posedge clk)
begin
q = d;
end


always@(a or q)
begin
out1 = (q & a);
end

endmodule

 

[lostinxlation]

How about this ?

module asg1(d, clk, a, out1);

input d, a, clk;
reg q;

output out1;
reg out1;

wire d = q;

always@(posedge clk)
begin
q <= d;
end


always@(a or q)
begin
out1 = (q & a);
end

endmodule

Certainly, it is possible to make a netlist for this logic, but not sure if synthesis tool likes this logic. The issue is the flop has neither of reset value nor new value comming from D input, so the flop has a unknown value, and nowadays, synthesis tool is pretty smart to catch this type of the problem. In the real world, you don't want to make such a circuit.

 

[reachmagi]

is it possible to declare d input that way..

i mean, it was declared as input d;
and
wire d = q;

is this possible?
if i try to synthesize in xilinx i get the following error:
Invalid use of input signal <d> as target.

 

[lostinxlation]

wire d = q; is legit, but if it doesn't work, how about

wire d;
assign d = q ;

but why do you want make this logic ? This doesn't make a logical sense, since you'll never know what value this flop will get. The tool probably doesn't like it.

 

[reachmagi]

thats my assignment question...
i tried a lot of ways and did realize to synthesize a code for that particular code is not possible...

---------- Post added at 15:08 ---------- Previous post was at 15:07 ----------

thanks a lot 'lostinxlation'

---------- Post added at 15:36 ---------- Previous post was at 15:08 ----------

finally i could come up with the following synthesis-able code provided an extra reg driven by clock occurs:


module asg1(clk, a, out1);

input a, clk;
output out1;
reg q, temp, out1;
wire d;

assign d = temp;

always@(posedge clk)
begin
q <= d;
temp <= q;
end


always@(a or q)
begin
out1 = (q & a);
end

endmodule

 

[FvM]

The code is not correct according to the circuit, because it implements two DFF instead of one. Your schematic corresponds to this (obviously meaningless) code.

always@(posedge clk)
begin
q = q;
end

May it be the case, that q <= ~q has been intended?

P.S.: The synthesis result will be implementation dependent. For a FPGAs with default initial register state of 0 (power on reset), q will be assumed 0, and the output stuck to zero. This also happens with your second idea. In simulation, q will stay at 'U' (uninitialized).

 

[reachmagi]

if i give q <= q;
the d input is not used at all so the circuit cannot be deduced..

 

[FvM]

Declaring d as input has been wrong anyway. d is no input to the circuit. You corrected this in your second example.

Setting q <= q gives the correct RTL netlist according to your schematic, also assign d = q gives the same result.



Your second code results in this RTL netlist



But, in synthesis, both reduce to a zero logic gate level

 

[reachmagi]

ok, i tried the following code..as you said,

module asg1(clk, a, out1);
input a, clk;
output out1;
reg q, out1;
wire d;

assign d = q;

always@(posedge clk)
begin
q <= q;
end

always@(a or q)
begin
out1 = (q & a);
end
endmodule

and these are the warnings i got while i tried doing the synthesis:
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <q> is used but never assigned. This sourceless signal will be automatically connected to value 0.

Signal <d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.


so the RTL schematic had no FF...

 

[FvM]

You can either write

assign d = q;
always@(posedge clk)
begin
q <= d;
end

or

always@(posedge clk)
begin
q <= q;
end

Both are equivalent, reduced to q = 0 in synthesis.

 

[lostinxlation]

Your best bet is defining d as an input and q as an output of that module, and synctheizing it. Then have a wrapper module that connect q and d.

Like i said, the synthesis tool may not proceed with a logic that doesn't make sense. That's a safeguard to prevent the designers from creating a faulty logic.

Synthesize the first code below, and use it with the 2nd code as a final netlist.

module sub_asg1 (clk, a, d, q, out1);
input clk, a, d;
output q, out1;

always @ (posedge clk)  q <= d;
assign  out1 = q & a;
endmodule

modue asg1 (clk, a, out1);
input clk, a;
output out1;

sub_asg1 i0 (.clk(clk), .d(q), .q(q), .a(a), out1(out1));
endmodule