Certainly, it is possible to make a netlist for this logic, but not sure if synthesis tool likes this logic. The issue is the flop has neither of reset value nor new value comming from D input, so the flop has a unknown value, and nowadays, synthesis tool is pretty smart to catch this type of the problem. In the real world, you don't want to make such a circuit.
wire d = q; is legit, but if it doesn't work, how about
wire d;
assign d = q ;
but why do you want make this logic ? This doesn't make a logical sense, since you'll never know what value this flop will get. The tool probably doesn't like it.
The code is not correct according to the circuit, because it implements two DFF instead of one. Your schematic corresponds to this (obviously meaningless) code.
Code:
always@(posedge clk)
begin
q = q;
end
May it be the case, that q <= ~q has been intended?
P.S.: The synthesis result will be implementation dependent. For a FPGAs with default initial register state of 0 (power on reset), q will be assumed 0, and the output stuck to zero. This also happens with your second idea. In simulation, q will stay at 'U' (uninitialized).
module asg1(clk, a, out1);
input a, clk;
output out1;
reg q, out1;
wire d;
assign d = q;
always@(posedge clk)
begin
q <= q;
end
always@(a or q)
begin
out1 = (q & a);
end
endmodule
and these are the warnings i got while i tried doing the synthesis:
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Signal <q> is used but never assigned. This sourceless signal will be automatically connected to value 0.
Signal <d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Your best bet is defining d as an input and q as an output of that module, and synctheizing it. Then have a wrapper module that connect q and d.
Like i said, the synthesis tool may not proceed with a logic that doesn't make sense. That's a safeguard to prevent the designers from creating a faulty logic.
Synthesize the first code below, and use it with the 2nd code as a final netlist.
Code:
module sub_asg1 (clk, a, d, q, out1);
input clk, a, d;
output q, out1;
always @ (posedge clk) q <= d;
assign out1 = q & a;
endmodule