Need Verilog code for sine wave

[qammer]

generate sine waves using vhdl

hi
i need verilog code for sine wave. plz send me code or tell idea to implement in verilog. my id is mideaker.86@gmail.com

 

[deepu_s_s]

student verilog sine

Hi
Please find the attached copy of the document. If it helps you....Please press on helped me ............

 

[echo47]

verilog sine wave

Verilog provides the $sin() system function.

 

[FvM]

synthesisable sine wave generator

Verilog provides the $sin() system function

I expect, that there should be a similar option, but I didn't find it in any of my used Verilog references (e. g. Synopsys, IEEE standard). That't not a problem to me, cause I'm mainly using VHDL, but it would be interesting to know. Do you know, if a similar Verilog construct exists for infering a sine look-up-table ROM as I demonstrated for VHDL?
Should I consult a separate system function manual to know about $sin().

P.S.: I found, that $sin() is a Verilog-2005 feature. Although it is apparently known in Altera Quartus, it seems to be unsupported for generating tables. I wonder if it is supported in Xilinx tools for this purpose?

 

[echo47]

vhdl code for sine wave

Xilinx XST doesn't yet support those handy Verilog math functions, even for constant calculation. The XST 10.1i User Guide gives a short list of different supported system tasks and functions, and then says "all others ignored". Rumors suggest that may change in Version 11. ModelSim has supported $sin() for years. $sin() is listed in section 17.11 of IEEE Std 1365-2005.

 

[kytay2]

sine wave generation using verilog code

it already has the $sin() function!

 

[amsut]

verilog $sin

it already has the $sin() function!

But this function is not synthesizable ... I know 1 lame trick to generate the sine wave from DSP concept but really i havent never got enough courage to convert this trick to HDL , it was too long .

 

[Old Nick]

math_real sin

There's a synthesisable sine wave generator in VHDL on this site,

https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/

I don't know if you can steal some idea's from there.

 

[amsut]

sine lockup table

There's a synthesisable sine wave generator in VHDL on this site,

https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/

I don't know if you can steal some idea's from there.

Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....

 

[Old Nick]

vhdl code for sine wave generator

There's a synthesisable sine wave generator in VHDL on this site,

https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/

I don't know if you can steal some idea's from there.

Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....

Has one had a bad day?

I was trying to help the original poster, not offend you!

 

[FvM]

vhdl sine wave generoator code

The term synthesisable sine wave generator may cause some confusion for those not familiar with HDL NCO and similar applications. To my opinion, many applications dealing with sine waves are excactly needing look-up-tables and synthesisable just means an effective way to generate and use a look-up-table. One may use script languages as the said doulos example or HDL code only, as I prefer. The Verilog $sin() support has been discussed in this regard, with the result, that it's missing in present versions of Altera and Xilinx synthesis tools. In VHDL, sine look-up-tables can be generated without a script roundabout at least by Altera Quartus.

Synthesisable may also be understood as calculating a sine function value without a lock-up-table, but it would require a numeric processor performing an iterative solution. This way, it can be synthesisable as well, by using an IP core, not just a simple HDL function as $sin() in Verilog or IEEE.MATH_REAL.SIN in VHDL.

As in in many EDAboard discussion, the original question has been rather ambiguous. There's no reason to get upset if someone understands it different, I think.

 

[amsut]

vhdl code to generate sinwave

There's a synthesisable sine wave generator in VHDL on this site,

https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/

I don't know if you can steal some idea's from there.

Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....

Has one had a bad day?

I was trying to help the original poster, not offend you!

Oh ! So it was fine,my friend. Misunderstood in the begining makes us becomes closer friend in future. But seriously i can not enjoy the word "steal" you used .... Have a nice day man .

Added after 15 minutes:

Xilinx XST doesn't yet support those handy Verilog math functions, even for constant calculation. The XST 10.1i User Guide gives a short list of different supported system tasks and functions, and then says "all others ignored". Rumors suggest that may change in Version 11. ModelSim has supported $sin() for years. $sin() is listed in section 17.11 of IEEE Std 1365-2005.

Master Echo47, if i do not mistake ModelSim simulation is based on the generation of equivalent C++ code for the design right ? And this C code will operate with the ModelSim available package, say 1164 or Math Real to generate the simulation output. So even if you r successfully simulated it wont mean that your design is synthesizable and layout extractable .... Hope i havent understand anything in wrong way.

 

[echo47]

vhdl sine wave sin rom

Hi amsut, I don't know how ModelSim works internally, but I've never seen any clues that it uses C++ or other intermediate language when compiling HDL. It compiles fast, so I'm guessing it translates your HDL directly into some internal executable format, and then runs it.

Simulation tools usually have much fuller support of HDL languages than synthesis tools. Your original question asked about Verilog only, and didn't mention synthesis or simulation.

I'm looking forward to the day when Xilinx adds math functions and floating point support to XST's Verilog 'initial' blocks. Then I will be able to fill a ROM with a math table such as a sinewave by writing a simple two-line 'for' loop. Right now, I use C or MATLAB or my ModelSim testbench to compute the math and generate a file containing Verilog initialization statements (see `include) or numerical data (see $readmemb and $readmemh) that are supported by XST.

If you wish to compute sin(x) by using something like Taylor series math, and have it be synthesizable using today's FPGA tools, then that's a different problem.

 

[FvM]

sine wave generator coding using vhdl

Amsut didn't raise the original question. He just got upset about designating sine table usage as synthesisable code. The original intention is still unknown, although I would understand code for sine wave as table generation, e. g. for a NCO.

 

[echo47]

sine wave generating vhdl code

Oops, I accidentally typed "your original question" (incorrectly referring to Amsut) instead of "the original question" (referring to qammer's question). Sorry for the mix-up.

 

[atena]

vhdl code for sine wave generation

Hi amsut, I don't know how ModelSim works internally, but I've never seen any clues that it uses C++ or other intermediate language when compiling HDL. It compiles fast, so I'm guessing it translates your HDL directly into some internal executable format, and then runs it.

Simulation tools usually have much fuller support of HDL languages than synthesis tools. Your original question asked about Verilog only, and didn't mention synthesis or simulation.

I'm looking forward to the day when Xilinx adds math functions and floating point support to XST's Verilog 'initial' blocks. Then I will be able to fill a ROM with a math table such as a sinewave by writing a simple two-line 'for' loop. Right now, I use C or MATLAB or my ModelSim testbench to compute the math and generate a file containing Verilog initialization statements (see `include) or numerical data (see $readmemb and $readmemh) that are supported by XST.

If you wish to compute sin(x) by using something like Taylor series math, and have it be synthesizable using today's FPGA tools, then that's a different problem.

Sure, this is a big disadvantages that initial block for the output and inout cant be synthesized in the design, especially for those design which used digital feedback concept.
From my opinion, the maximum floating point support can only be the embeded-conversion function to directly convert floating point ip to standar digital form of IEEE ... The rest potentialy we have to do ourself ...

Beside, by refering to C++, i think Amsut want to refer to the Simulation with ModelSim but not Compilation ....

 

[Old Nick]

verilog ieee.math_real.sin

There's a synthesisable sine wave generator in VHDL on this site,

https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/

I don't know if you can steal some idea's from there.

Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....

Has one had a bad day?

I was trying to help the original poster, not offend you!

Oh ! So it was fine,my friend. Misunderstood in the begining makes us becomes closer friend in future. But seriously i can not enjoy the word "steal" you used .... Have a nice day man .

Perfectly acceptable use of the word steal; it is not meant in a bad way when used in that manner. I am a native English speaker and thus maybe a bit more accustomed in the subtle nuances of this language. It's probably better not to correct (or read too much into) peoples usage of language on a site of which most of the users are not conversing in their mother tounge anyway.

But cheers anyway.

Nick

 

[vipinlal]

sin wave code

if you want a synthesisable code for sine wave generator get it from here..
https://vhdlguru.blogspot.com/2010/03/simple-sine-wave-generator-in-vhdl.html

 

[bigdogguru]

Re: sin wave code

Some of the early C compilers for µPs without math coprocessors generated sin() using the Taylor Series

 sin(x) = x - x^3/3! + x^5/5! - x^7/7!....

Just extend the series out to the precision you need and the repeatablity of the series lends itself to loops.

Although today most software routines use CORDIC algorithms followed up by a Taylor Approximation.

If I remember correctly the CORDIC algorithms are calculated more efficiently by hardware without inherit hardware multipliers, such as most FPGAs.