I expect, that there should be a similar option, but I didn't find it in any of my used Verilog references (e. g. Synopsys, IEEE standard). That't not a problem to me, cause I'm mainly using VHDL, but it would be interesting to know. Do you know, if a similar Verilog construct exists for infering a sine look-up-table ROM as I demonstrated for VHDL?Verilog provides the $sin() system function
But this function is not synthesizable ... I know 1 lame trick to generate the sine wave from DSP concept but really i havent never got enough courage to convert this trick to HDL , it was too long .kytay2 said:it already has the $sin() function!
Old Nick said:There's a synthesisable sine wave generator in VHDL on this site,
https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/
I don't know if you can steal some idea's from there.
amsut said:Old Nick said:There's a synthesisable sine wave generator in VHDL on this site,
https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/
I don't know if you can steal some idea's from there.
Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....
Old Nick said:amsut said:Old Nick said:There's a synthesisable sine wave generator in VHDL on this site,
https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/
I don't know if you can steal some idea's from there.
Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....
Has one had a bad day?
I was trying to help the original poster, not offend you!
echo47 said:Xilinx XST doesn't yet support those handy Verilog math functions, even for constant calculation. The XST 10.1i User Guide gives a short list of different supported system tasks and functions, and then says "all others ignored". Rumors suggest that may change in Version 11. ModelSim has supported $sin() for years. $sin() is listed in section 17.11 of IEEE Std 1365-2005.
Sure, this is a big disadvantages that initial block for the output and inout cant be synthesized in the design, especially for those design which used digital feedback concept.echo47 said:Hi amsut, I don't know how ModelSim works internally, but I've never seen any clues that it uses C++ or other intermediate language when compiling HDL. It compiles fast, so I'm guessing it translates your HDL directly into some internal executable format, and then runs it.
Simulation tools usually have much fuller support of HDL languages than synthesis tools. Your original question asked about Verilog only, and didn't mention synthesis or simulation.
I'm looking forward to the day when Xilinx adds math functions and floating point support to XST's Verilog 'initial' blocks. Then I will be able to fill a ROM with a math table such as a sinewave by writing a simple two-line 'for' loop. Right now, I use C or MATLAB or my ModelSim testbench to compute the math and generate a file containing Verilog initialization statements (see `include) or numerical data (see $readmemb and $readmemh) that are supported by XST.
If you wish to compute sin(x) by using something like Taylor series math, and have it be synthesizable using today's FPGA tools, then that's a different problem.
amsut said:Old Nick said:amsut said:Old Nick said:There's a synthesisable sine wave generator in VHDL on this site,
https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/
I don't know if you can steal some idea's from there.
Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in fact that code is quite simple but remember before creating it you have to generate the sine package, and this is a massive work, because this package will contain all the quantized value of a sine function in 1 period, that's why i said that i never will to make it ....
Has one had a bad day?
I was trying to help the original poster, not offend you!
Oh ! So it was fine,my friend. Misunderstood in the begining makes us becomes closer friend in future. But seriously i can not enjoy the word "steal" you used.... Have a nice day man .
sin(x) = x - x^3/3! + x^5/5! - x^7/7!....
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