Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Need Verilog code for pulse counter

Status
Not open for further replies.

rakko

Full Member level 4
Joined
Jun 1, 2001
Messages
233
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,298
Location
mozambic
Activity points
2,065
anyone has the verilog code for a pulse counter that counts a varying pulse synchronous to another clock?
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
638
Reputation
1,274
Reaction score
89
Trophy points
1,328
Location
USA
Activity points
33,176
pulse counter

What do you want to count - number of pulses, pulse width, pulse period?
What is that other clock doing?
Maybe draw a timing diagram of what you mean.
 

rakko

Full Member level 4
Joined
Jun 1, 2001
Messages
233
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,298
Location
mozambic
Activity points
2,065
Re: pulse counter

I want to count the number of pulses. The master clock is running at a fixed 25mhz frequency. The pulses are much slower in the order of khz and do not have even duty cycles. they could be as fast as a few mhz to slow as a few khz.
 

Nandy

Advanced Member level 4
Joined
Dec 16, 2005
Messages
116
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,298
Location
San Jose CA
Activity points
2,399
Re: pulse counter

Attached verilog file of pulse counter.

Added after 2 minutes:

Resend in plain text.

module counter(sclk, fclk, rstn, counter);
input sclk, fclk ,rstn;
output counter;

wire syn_sclk
//you can search web to find "pulse synchronizer" logic
// Or I will come up one later.
psync_cell u_pc(.d(sclk), .clk(fclk), .rstn(rstn), .o(syn_sclk));
reg [15] counter;
always @(posedge fclk or negedge rstn)
if(!rstn) counter <= 0;
else if(syn_sclk) counter <= counter + 1;

endmodule

Added after 2 hours 18 minutes:

Check here for pulse synchronizer schematic.
https://www.nandigits.com/p85.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.[/url]
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top