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need to convert it to vhdl

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amritmani

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hi
I have the folloing decoder code in C can anyone please send me the code in VHdl which decode a input file and read it from memory. I urgently required that. I am new

Code:
/*	Filename:     GTRLE35.C
	
	Description:  A Run-Length Encoding (RLE) Implementation.
	
	How it works:

		If there is a run of bytes, two bytes are output
		and then the next number of runs are encoded.

		Example:   abcddddd
		Encoding:  abcdd3	{regard '3' as a value.}

	Written by:   Gerald Tamayo
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

void copyright (void);
void rle_encode (FILE *in, FILE *out);
void rle_decode (FILE *in, FILE *out);

int main (int argc, char *argv[])
{
	FILE *in, *out;
	
	if (argc < 3 || argc > 4){
		fprintf(stderr, "\n Run Length Encoding (RLE) implementation.\n" 
			"\n Usage : gtrle inputfile outputfile [/d]");
		copyright();
		return 0;
	}
	
	in = fopen(argv[1], "rb");
	if (!in) {
		fprintf(stderr, "\n Error opening input file!");
		copyright();
		return 0;
	}
	out = fopen(argv[2], "wb");
	if (!out) {
		fprintf(stderr, "\n Error opening output file!");
		copyright();
		return 0;
	}

	if (argc == 4){
		if (!strcmp(argv[3], "/d") || !strcmp(argv[3], "/D")){
			fprintf(stderr, "\n Run-Length decoding...");
			rle_decode(in, out);
		}
		else {
			fprintf(stderr, "\n Error! Unknown: \"%s\"\n", argv[3]);
			return 0;
		}
	}
	else {
		fprintf(stderr, "\n Run-Length encoding...");
		rle_encode(in, out);
	}
	fprintf(stderr, "complete.\n");
	
	if (in ) fclose(in);
	if (out) fclose(out);
	return 0;
}

void rle_encode (FILE *in, FILE *out)
{
	int c, prev, rle_cnt = 0;

	/* get first byte and assign it as the *previous* byte. */
	if ((c=getc(in)) != EOF) {
		putc((unsigned char) c, out);
		prev = c;
	}
	else return;

	while ((c=getc(in)) != EOF) {
		if (c != prev) {
			/* if there's a run, encode it. */
			if (rle_cnt) {
				putc((unsigned char) prev, out);
				putc((unsigned char) rle_cnt-1, out);
				rle_cnt = 0;
			}

			/* then encode the new byte. */
			putc((unsigned char) c, out);
			prev = c;
		}
		else {
			/* increment count; if count == 256, quickly encode it. */
			if ((++rle_cnt) == 256) {
				/* the first byte of the 256 bytes. */
				putc((unsigned char) prev, out);

				/* the next 255 bytes. (rle_cnt-1) == 255. */
				putc((unsigned char) 255, out);
				rle_cnt = 0;
			}
		}
	}

	/* if there's a run, encode it. */
	if (rle_cnt) {
		putc((unsigned char) prev, out);
		putc((unsigned char) rle_cnt-1, out);
	}
}

void rle_decode (FILE *in, FILE *out)
{
	int c, prev, rle_cnt;

	/* get first byte and assign it as the *previous* byte. */
	if ((c=getc(in)) != EOF) {
		prev = c;
		putc((unsigned char) c, out);
	}
	else return;

	while ((c=getc(in)) != EOF) {
		if (c == prev) {
			putc((unsigned char) prev, out);
			/*	output the next "run" of bytes, as
				stored in the rle_cnt variable.
			*/
			if ((rle_cnt = getc(in)) != EOF) {
				while(rle_cnt--) {
					putc((unsigned char) prev, out);
				}
			}
			else break;
		}
		else {
			putc((unsigned char) c, out);
			prev = c;
		}
	}
}

void copyright (void)
{
	fprintf(stderr, "\n\n Written by: Gerald Tamayo\n");
}
to this field please help
 
Last edited by a moderator:

SPARK C-to-VHDL

SPARK takes behavioral ANSI-C code as input, schedules it using speculative code motions and loop transformations, runs an interconnect-minimizing resource binding pass and generates a finite state machine for the scheduled design graph. Finally, a backend code generation pass outputs synthesizable register-transfer level (RTL) VHDL.

Download

h**p://mesl.ucsd.edu/spark/download/
 

this Spark is Not working for my code. it is giving the following error........
please help if anyone has any idea about how to remove this error


SPARK Version 1.2 (built on Feb 4 2004 17:31:10) is initializing ... Done!
"/usr/include/gnu/stubs.h", line 7: catastrophic error: could not open source
file "gnu/stubs-32.h"
# include <gnu/stubs-32.h>
^

ERROR: assertion failed!
Expr: EDG error
Dir: <no dir info>
File: host_envir.c
Line: 1497
spark: SparkSystem.cpp:99: void _sparkAssert(char*, char*, unsigned int): Assertion `0' failed.
Aborted (core dumped)

---------- Post added at 12:00 ---------- Previous post was at 11:59 ----------

SPARK is giving the following error....SPARK Version 1.2 (built on Feb 4 2004 17:31:10) is initializing ... Done!
"/usr/include/gnu/stubs.h", line 7: catastrophic error: could not open source
file "gnu/stubs-32.h"
# include <gnu/stubs-32.h>
^

ERROR: assertion failed!
Expr: EDG error
Dir: <no dir info>
File: host_envir.c
Line: 1497
spark: SparkSystem.cpp:99: void _sparkAssert(char*, char*, unsigned int): Assertion `0' failed.
Aborted (core dumped)
 

this Spark is Not working for my code. it is giving the following error........
please help if anyone has any idea about how to remove this error


SPARK Version 1.2 (built on Feb 4 2004 17:31:10) is initializing ... Done!
"/usr/include/gnu/stubs.h", line 7: catastrophic error: could not open source
file "gnu/stubs-32.h"
# include <gnu/stubs-32.h>
^

ERROR: assertion failed!
Expr: EDG error
Dir: <no dir info>
File: host_envir.c
Line: 1497
spark: SparkSystem.cpp:99: void _sparkAssert(char*, char*, unsigned int): Assertion `0' failed.
Aborted (core dumped)

---------- Post added at 12:00 ---------- Previous post was at 11:59 ----------

SPARK is giving the following error....SPARK Version 1.2 (built on Feb 4 2004 17:31:10) is initializing ... Done!
"/usr/include/gnu/stubs.h", line 7: catastrophic error: could not open source
file "gnu/stubs-32.h"
# include <gnu/stubs-32.h>
^

ERROR: assertion failed!
Expr: EDG error
Dir: <no dir info>
File: host_envir.c
Line: 1497
spark: SparkSystem.cpp:99: void _sparkAssert(char*, char*, unsigned int): Assertion `0' failed.
Aborted (core dumped)

SPARK Does have some restriction on C Accepted as input



No support for pointers. However, arrays and array accesses of the type arr[index variable expression] are
supported. Also, passing arguments by reference to a function is also supported.

No support for function recursion.

No support for irregular jumps through goto. Some of these can be resolved in a state machine, but they
adversely affect our ability to apply transformations

No support for break and continue. In general, it is possible to convert a program with breaks and continues
into a program without them

No support for multi-dimension arrays. Multi-dimensional arrays can be reduced manually to singledimensional
arrays. For example: consider an array a[N][M]. This can be re-declared as a[N*M]. Any
access to a[j] then becomes a[i*M+j]


Poor/no support for structs and unions. In general, structs are currently not synthesizable. Also, no VHDL
generation for user-defined data types.


Poor support for expressions of type (a ? b : c). We advise changing this expression to the following
statement:
if (a) b
else c
 

you will not get a very good result doing a direct c -> VHDL conversion (if it even works at all). Unless you've taken hardware into consideration when you write the C, you'll have really bad VHDL. Loops do not convert to VHDL very well at all.

I suggest you start reading up on hardware design.
 

As TrickyDicky said,if you want a better design ,it's good switch to VHDL/Verilog and most of these
C to HDL cannot produce efficient code.most of them have restrictions and they generally based on some
sort of templates .

example

Code:
[syntax=c]void main()
{
     
     int a=4;
     int b=5;
     int c=0;
	 	   c=a+b;
     
   }[/syntax]


Output

Code:
[syntax=vhdl]-- Automatically generated by the SPARK High-Level Synthesis System
-- Wed Nov 30 13:28:04 2011, source file : prog.c

-- 'SPARK' should be defined as the user package
PACKAGE spark_pkg is
  TYPE integer_vector IS ARRAY ( NATURAL RANGE <>) OF integer;
  TYPE boolean_vector IS ARRAY ( NATURAL RANGE <>) OF boolean;
  FUNCTION integer_wired_or ( arr_int : integer_vector ) RETURN integer;
  FUNCTION boolean_wired_or ( arr_bool : boolean_vector ) RETURN boolean;
  SUBTYPE wiredOrInt IS integer_wired_or integer;
  SUBTYPE wiredOrBoolean IS boolean_wired_or boolean;
END spark_pkg;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;

PACKAGE BODY spark_pkg IS
  FUNCTION integer_wired_or ( arr_int : integer_vector ) RETURN integer is
    -- pragma resolution_method wired_or
    variable i : integer;
    variable returnVal : std_logic_vector(15 downto 0);
    variable arr_int_std_logic_vec : std_logic_vector(15 downto 0);
  BEGIN
    returnVal := (others => '0');
    for i in arr_int'range loop
      arr_int_std_logic_vec := conv_std_logic_vector(arr_int(i), 16);
      returnVal := returnVal or arr_int_std_logic_vec;
    end loop;
    RETURN conv_integer(returnVal);
  END integer_wired_or;

  FUNCTION boolean_wired_or ( arr_bool : boolean_vector ) RETURN boolean is
    -- pragma resolution_method wired_or
    variable i : integer;
    variable returnVal : boolean;
  BEGIN
    returnVal := FALSE;
    for i in arr_bool'range loop
      returnVal := returnVal or arr_bool(i);
    end loop;
    RETURN returnVal;
  END boolean_wired_or;
end spark_pkg;

library IEEE;
library DWARE,SYNOPSYS;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use SYNOPSYS.attributes.all;


library work;
use work.spark_pkg.all;


ENTITY main IS 
port(
  CLOCK : IN std_logic ;
  RESET : IN std_logic ;
  done : OUT std_logic );
END main;

ARCHITECTURE rtl OF main IS

  signal a : wiredOrInt range -32767 to 32768 ;
  signal b : wiredOrInt range -32767 to 32768 ;
  signal c : wiredOrInt range -32767 to 32768 ;
  signal sT0_11 : wiredOrInt range -32767 to 32768 ;

  -- Statistics collected about this Schedule
  -- Scheduled with the following resources 
  -- 2 ALU, 1 MUL, 2 CMP, 2 SHFT, 2 ARR, 5 LOGIC, 5 GATE, 2 ALLCALLS, 
  -- Declarations of the 5 states in routine main
  subtype StateType is std_logic_vector(4 downto 0);
  CONSTANT S_0 : std_logic_vector(4 downto 0) := "00001";
  CONSTANT S_1 : std_logic_vector(4 downto 0) := "00010";
  CONSTANT S_2 : std_logic_vector(4 downto 0) := "00100";
  CONSTANT S_3 : std_logic_vector(4 downto 0) := "01000";
  CONSTANT S_4 : std_logic_vector(4 downto 0) := "10000";
  signal CURRENT_STATE : StateType;
  signal NEXT_STATE : StateType;
  BEGIN
    SYNC: PROCESS
    BEGIN
      wait until CLOCK'event and CLOCK = '1';
      if reset = '1' then
        CURRENT_STATE <= S_0;
        done <= '0';
      else
        CURRENT_STATE <= NEXT_STATE;
        if CURRENT_STATE /= S_0 and NEXT_STATE = S_0 then
          done <= '1';
        end if;
      end if;   -- if reset check
    END PROCESS;   -- SYNC Process

    FSM: PROCESS(CURRENT_STATE, sT0_11)
    BEGIN
      NEXT_STATE <= CURRENT_STATE;
      if CURRENT_STATE(0) = '1' then
        NEXT_STATE <= S_1;
      elsif CURRENT_STATE(1) = '1' then
        NEXT_STATE <= S_2;
      elsif CURRENT_STATE(2) = '1' then
        NEXT_STATE <= S_3;
      elsif CURRENT_STATE(3) = '1' then
        NEXT_STATE <= S_4;
      elsif CURRENT_STATE(4) = '1' then
        if sT0_11 then
          NEXT_STATE <= S_3;
        else  -- sT0_11        
          NEXT_STATE <= S_0;
        end if; -- conditions
      END if;  -- if (CURRENT_STATE)
    END PROCESS;   -- FSM Process

    DP: PROCESS

    BEGIN
      wait until CLOCK'event and CLOCK = '1';
      if reset = '1' then
        sT0_11 <= FALSE;
      else   -- else of   if reset
        if CURRENT_STATE(0) = '1' then
          a  <=  0;
        elsif CURRENT_STATE(1) = '1' then
          b  <=  0;
        elsif CURRENT_STATE(2) = '1' then
          c  <=  0;
        elsif CURRENT_STATE(3) = '1' then
          sT0_11  <=  1;
        elsif CURRENT_STATE(4) = '1' then
          if sT0_11 then
            c  <=  (a + b);
          end if; -- conditions
        END if;  -- if (CURRENT_STATE)
      end if;   -- end of   if reset
    END PROCESS;   -- DP Process

END rtl;
[/syntax]
 

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