Hi All,
I have to write the scrambler code in verilog. The scrambler is LFSR(Linear Feedback Shift Register) based.
The 23-bit polynomial for the LFSR is G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1
The main problem I am facing is finding the value of LFSR after 8 serial clocks (1 bit advanced in each clock).
There are 2 things here:
1. I need to have the scrambled value for the 8 bit data input to the scrambler
2. I need to know the next value of LFSR after the data input to it is scrambled completely
The next value of LFSR will be obtained after 8 clocks since input data is 8-bit
I have the code for the 16-bit polynomial G(X)=X16+X5+X4+X3+1
The code is like this:
//----------------------------------------------------------------------
// function data_scramble
// This function deals with scrambling of data byte given as input.
//----------------------------------------------------------------------
function [7:0] data_scramble;
input [7:0] inbyte; // Data to be scrambled
reg [15:0] temp_new;
reg [15:0] temp;
reg [7:0] scrbyte; // Scrambled Data
begin
//----------------------------------------------------------------------
// Generation of scrbyte (Scrambled Data)
//----------------------------------------------------------------------
// Store the current lfsr value in a temp variable
temp = lfsr_scr;
A comfortable way is to use the standard (1 bit-shift lfsr) function and let the Verilog compiler calculate an iteration over 8 clocks. The tool is smart enough to do this for you.
The first step is to write a Galois feedback form of your 23-Bit LFSR code.
The second is to put an for () iteration loop around it and repeat the code 8 times. Blocking assignment must be used for LFSR register in this case.