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#### aman_geek

##### Newbie level 3
lfsr code

Hi All,
I have to write the scrambler code in verilog. The scrambler is LFSR(Linear Feedback Shift Register) based.
The 23-bit polynomial for the LFSR is G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1
The main problem I am facing is finding the value of LFSR after 8 serial clocks (1 bit advanced in each clock).

There are 2 things here:
1. I need to have the scrambled value for the 8 bit data input to the scrambler
2. I need to know the next value of LFSR after the data input to it is scrambled completely
The next value of LFSR will be obtained after 8 clocks since input data is 8-bit

I have the code for the 16-bit polynomial G(X)=X16+X5+X4+X3+1
The code is like this:

//----------------------------------------------------------------------
// function data_scramble
// This function deals with scrambling of data byte given as input.
//----------------------------------------------------------------------
function [7:0] data_scramble;
input [7:0] inbyte; // Data to be scrambled
reg [15:0] temp_new;
reg [15:0] temp;
reg [7:0] scrbyte; // Scrambled Data
begin

//----------------------------------------------------------------------
// Generation of scrbyte (Scrambled Data)
//----------------------------------------------------------------------
// Store the current lfsr value in a temp variable
temp = lfsr_scr;

scrbyte[0] = inbyte[0]^temp[15];
scrbyte[1] = inbyte[1]^temp[14];
scrbyte[2] = inbyte[2]^temp[13];
scrbyte[3] = inbyte[3]^temp[12];
scrbyte[4] = inbyte[4]^temp[11];
scrbyte[5] = inbyte[5]^temp[10];
scrbyte[6] = inbyte[6]^temp[ 9];
scrbyte[7] = inbyte[7]^temp[ 8];

//----------------------------------------------------------------------
// Generation of temp_new (LFSR value after 8 serial clocks)
//----------------------------------------------------------------------
temp_new[ 0] = temp[ 8];
temp_new[ 1] = temp[ 9];
temp_new[ 2] = temp[10];
temp_new[ 3] = temp[11] ^ temp[ 8];
temp_new[ 4] = temp[12] ^ temp[ 9] ^ temp[ 8];
temp_new[ 5] = temp[13] ^ temp[10] ^ temp[ 9] ^ temp[ 8];
temp_new[ 6] = temp[14] ^ temp[11] ^ temp[10] ^ temp[ 9];
temp_new[ 7] = temp[15] ^ temp[12] ^ temp[11] ^ temp[10];
temp_new[ 8] = temp[ 0] ^ temp[13] ^ temp[12] ^ temp[11];
temp_new[ 9] = temp[ 1] ^ temp[14] ^ temp[13] ^ temp[12];
temp_new[10] = temp[ 2] ^ temp[15] ^ temp[14] ^ temp[13];
temp_new[11] = temp[ 3] ^ temp[15] ^ temp[14];
temp_new[12] = temp[ 4] ^ temp[15];
temp_new[13] = temp[ 5];
temp_new[14] = temp[ 6];
temp_new[15] = temp[ 7];
lfsr_scr = temp_new;
data_scramble = scrbyte ;
end
endfunction // data_scramble

I need to write the similar code for the 23 bit scrambler polynomial described above.

Thanks

#### FvM

##### Super Moderator
Staff member
lfsr scrambling polynomial

A comfortable way is to use the standard (1 bit-shift lfsr) function and let the Verilog compiler calculate an iteration over 8 clocks. The tool is smart enough to do this for you.

#### aman_geek

##### Newbie level 3
lfsr scrambler

Hey FvM,
Can you please elaborate on this...
Thanks.....

I have all the verilog simulators at my disposal: ModelSim, VCS, NCVerilog, QuestaSim....

#### FvM

##### Super Moderator
Staff member
bit scrambler c

The first step is to write a Galois feedback form of your 23-Bit LFSR code.
The second is to put an for () iteration loop around it and repeat the code 8 times. Blocking assignment must be used for LFSR register in this case.

### aman_geek

points: 2

#### aman_geek

##### Newbie level 3
scrambler polynomial lfsr

Thanks Fvm.....
I'll try your approach and get back to this thread if I need more help.

#### OutputLogic

##### Junior Member level 2
need for scrambler

There is an online tool that can generate scrambler Verilog or VHDL code. It's on http://outputlogic.com

Hope it helps

#### jjww110

##### Full Member level 5
lfsr bit scrambler

refer to sata spec!!

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