The description document that you provide explains pretty much everything with detail. If you want an overview of what is happening, I can tell you.
Is a flyback inverter controlled by PWM, it has dead time control and non-overlapping provided by IC5/6/8. The IC1 is implementing an square wave oscillator which pulse width is controlled by the negative feedback loop and the controller implemented by IC12/13 that sense the output current and output voltage and generate an error signal and compare that against a reference. T5-8 are the predrivers or level shifters. T13/20/21/28 are the main power drivers.
That is the main loop, everything around it is support circuitry like the charge pump (IC10) used to regulate some internal VDDs. It has some overload protection implemented by IC9 and IC7.
The description document details more on the design choices for the values so give it another try to fully understand what is happening.