[SOLVED] Need suggestions for logic flow

[dpaul81]

Hi all,

I need to convert data from big-endian to small-endian and vice-versa.

So that would essentially be the MSB bit taking the position of LSB bit and the LSB bit goes to the MSB position. The bit in position MSB-1 would take the position LSB+1 and the bit in LSB+1 would take the MSB-1 position. This goes on for the other bits!

The data size that needs to be converted can be 8/16/32 bits, they will be residing in corresponding size registers before conversion.

The most important requirement is to use the least number of clock cycles (if 1 clock cycle is used, then that would be the best solution).

So please suggest me the best possible logic requiring LEAST number of clock cycles. I need to implement this in Verilog....but this is later! Must have the logic first!

Thanks in advance,
dpaul

 

[treqer]

reading permuted data produced with the same input from 8-16-32?

rather a permanent or switched

---------- Post added at 16:54 ---------- Previous post was at 16:48 ----------

what do you mean by a single cycle? if the data come in 8-bit, it is impossible to rearrange them into a single cycle.

 

[std_match]

Hi all,

I need to convert data from big-endian to small-endian and vice-versa.

So that would essentially be the MSB bit taking the position of LSB bit and the LSB bit goes to the MSB position. The bit in position MSB-1 would take the position LSB+1 and the bit in LSB+1 would take the MSB-1 position. This goes on for the other bits!

This is not a conversion, it is just a question of bit numbering, so it takes no time at all. The LSB is still the LSB regardless of endianess.

I don't know Verilog, but in VHDL you can assign directly between vectors with different bit numbering.

signal big_endian_vector : std_logic_vector(0 to 31);
signal little_endian_vector : std_logic_vector(31 downto 0);
 
little_endian_vector <= big_endian_vector;

 

[std_match]

Maybe I should clarify that

little_endian_vector <= big_endian_vector;

in this case is identical to

little_endian_vector(31) <= big_endian_vector(0);
little_endian_vector(30) <= big_endian_vector(1);
........
little_endian_vector(1) <= big_endian_vector(30);
little_endian_vector(0) <= big_endian_vector(31); -- This is the LSB in both vectors!

 

[j_andr]

if you mean just bit swapping, this is one possibility:

parameter  W = 8;

integer i;
 always @(posedge clk)
   for (i=0; i<W; i = i+1)
      out[i] <= in[W-1-i];

btw - std_match is right ...

---
have hun

 

[lostinxlation]

Just FYI.
What you are trying to do is a bit swapping, not endianness conversion.
Endianness applies on a byte basis, not a bit basis.

 

[permute]

I don't think you can use a loop variable as an index in verilog. At least I've had issues with XST. you might need to use a for-generate statement if that is the case.

for VHDL, the bitreversal can be a bit tricky. it might be fine if you want to serialize the data. But not if you need multiple output bits. eg, if both Din and Dout are "downto", and you have an intermediate "to" signal, nothing really happens. It maps the uppermost bit of din( din(31)) to the uppermost bit of the intermediate (sig(0)), then it maps the uppermost bit of the intermediate (sig(0)) back to the uppermost of dout (dout(31)).

 

[dpaul81]

Re: Need suggestions for logic flow - Endianness Conversion

1st of all my apologies for the misconception about Endianness! Thanks 'lostinxlation' for the clarification!

So what I essentially need is that, there r two systems interconnected by a bus-system and they have to exchange data. 32 bit data bus is used for info. exchange (32 bit address bus is there too).
One system uses Big-Endian format of storing data & the other one Small-Endian. So how do I do implement this conversion....in principle?

As per my understanding, when it comes to storing a 32 bit data, endianness comes to the picture(breaking up 32 bits into 4 eight-byte, etc., u all know). So when this data is placed in the bus system, how is this done? The MSB-Byte is placed first or the LSB-Byte?