need suggestion on circuit model for HBT on SOI

[skyhorse]

I have very interesting HBT devices fabricated on thin SOI.
The most interesting part is that by increasing substrate bias voltage, Rc decreases, breakdown voltage decreases, ft/fmax increases.
Now I am trying to build a circuit model for this device, unfortunately I am new to modeling. My starting questions:
1. Which circuit model is better: VBIC, Gummel-Poon, HiCUM? I know roughly how to extract the model parameters from my data.
2. How to model the substrate bias effects? Should I add sub-bias dependent Rc and capacitance for that purpose.
By the way, this is some intial work for academic purpose, not necessarily to be perfect for industry use.

Any suggestion is appreciated.

 

[unicum]

Hi

1. Which circuit model is better: VBIC, Gummel-Poon, HiCUM? I know roughly how to extract the model parameters from my data.

HICUM and MEXTRAM are much more advanced. VBIC and SPGM are almost the same. VBIC is SGPM replacement, anyway.

2. How to model the substrate bias effects? Should I add sub-bias dependent Rc and capacitance for that purpose.

These effects are caused by different physical reasons. You should model them separately in anyway.
unicum