High-level architectural synthesis and compilation techniques
1. Novel approaches in high-level synthesis of data-flow and stream processors
2. Novel approaches in automated design space exploration
3. Novel decision making methods in area of high-level architectural synthesis
4. Selection of Pareto-optimal computing architecture for given algorithm (task)
5. Architecture synthesis for reconfigurable embedded computing systems
6. Compilation techniques for adaptive and reconfigurable architectures
7. Dynamic compilation and runtime execution environments
Platforms for high-level synthesis support and design verification
8. FPGA platforms for rapid prototyping and design verification
9. Temporal partitioning of hardware resources in architectural synthesis of digital processing systems: Novel scheduling algorithms
10. Spatial partitioning of hardware resources in architectural synthesis of digital processing systems: Novel binding algorithms
11. High performance adaptive and reconfigurable architectures
12. Hardware/software trade-offs in hybrid architectures
13. Hardware acceleration through architecture reconfiguration