Sink0
Full Member level 6
- Joined
- Nov 25, 2009
- Messages
- 390
- Helped
- 37
- Reputation
- 74
- Reaction score
- 30
- Trophy points
- 1,308
- Location
- Sao Paulo, Brazil
- Activity points
- 4,186
Hi, i am implementing a Half-Duplex M-LVDS bus with a FPGA at each node running at 100Mbps. As it half-duplex and mult-drop i cant see a way to implement a syncronous tranmission (or am i wrong?) without using a clock line. I am planing on using some sort of encoding as manchester or 8b/10b, but i would still need to detect data. I am planing on using some low-end with a small footprint as a 100 pins cyclone. As i would need to oversample the port to detect incoming data, how can i oversample a 100 Mhz data using a 250 -300 Mhz clock... Any ideas? Or sugestions on how to solve that problem?