Ok, so I need to become bilingual, but this is just annoying me.
Can someone give me the SV equivolent of this VHDL:
Code:
signal ENDSIM : boolean := false;
process
begin
my_sig1 <= '0';
my_sig2 <= '1';
wait until reset = '0';
while not ENDSIM loop
--play around with my_sig1 and my_sig2;
wait until rising_edge(clk);
end loop;
wait;
end process;
I dont want to make the process sensitve to clock and reset, I would like it a process with no sensitivity list. If I can get my head around this, then stimulus generation should make more sense to me. This format allows much easier behavioural modelling.
bit ENDSIM = 1'b0;
logic my_sig1 = 1'b0;
logic my_sig2 = 1'b1;
always
begin
while (reset);
while (!ENDSIM)
begin
// playtime
@(posedge clk);
end // while (!ENDSIM)
end // always
Its a bit early for me so there could be some big flat forehead mistakes!
r.b.
I tried this, but all it seems to do is kill Questa:
Code:
always
begin : StimGen
data <= 0;
mu_ch_cnt <= 0;
wait (areset == 0) $display("Starting stimulus generation");
while (!KILLSIM)
begin
data <= data + 1;
mu_ch_cnt <= mu_ch_cnt + 1;
@(posedge clk);
end
$display("Stimulus Stopped");
disable StimGen;
end
It is hard to say, but KILLSIM is never set so it may run forever, and since you are using non-blocking assignments (<=) I am not sure what states data and mu_ch_cnt will take when. "data", for example, will not take the value of 0 until the simulation moved forward in time (i.e. at a clock edge). I am not sure if a wait statement will make that happen.
I would have expected it to work but perhaps someone you has used SV more extensively for verification could chime in.
Re: Need some VHDL -> System Verilog Conversion
It appears to get into an infinite loop somewhere, and needs to be killed via the task manager.
Killsim is defined and used here:
Code:
bit KILLSIM = 0;
initial
begin : ClockGen
clk = 0;
forever
begin
#(CLKPERIOD) clk = !clk;
//Force a timeout
if ( $time > (2*TIMEOUT*CLKPERIOD ) ) //x2 for rise and fall
begin
$display("Testbench timed out after %d clocks", TIMEOUT);
KILLSIM = 1;
disable ClockGen;
end
end
end
- - - Updated - - -
the problem may be the fact Im using an always rather than an initial block?
Re: Need some VHDL -> System Verilog Conversion
You could change to an initial block and try it. Or use a fork/join block where one fork is the timer and one is the sim, and the timer disables the sim fork (explicitly via a disable or by asserting KILLSIM) when the time period is reached. Then the sim block is neither initial or always, it is a fork.
Sorry for the quick (potentially unhelpful) comments, I am in meetings today...
Re: Need some VHDL -> System Verilog Conversion
In VHDL:
Code:
process
begin
-- some code
wait;
end
translates to Verilog
Code:
initial
begin
// some code
end
- - - Updated - - -
while (expression);
is an infinite loop if the expression is true. The correct translation is
Code:
bit ENDSIM = false;
initial
begin
my_sig1 <= 0;
my_sig2 <= 1';
wait(reset == 0);
while (! ENDSIM) begin : loop
//play around with my_sig1 and my_sig2;
@(posedge clk);
end