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Need some hints about getting pixel data from memory on FPGA

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win3y

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Hi, everybody!
I do not know how to code a module that have function to get pixel data such as current pixel and reference pixel from memomy for calculation motion estimation. Pls give me some advice to implement it. For example, the output of above module is pixel data that synchronize by clock pusle input.
Thank you very much.
 

nxtech

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Re: Need some hints about getting pixel data from memory on

Choose the FPGA you plan to use then look at the users guide for details on how to implement the on board memory.

E
 

    win3y

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darui

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You can broadcast current pixel or reference pixel.
Detials can be found in paper
K.M. Yang, M.T. Sun, and L. Wu, "A Family of VLSI Designs for the Motion Compensation Block-Matching Algorithm," IEEE Transactions on Circuits and Systems, pp. 1317-1325, Oct. 1989.

Liang-Gee Chen's team is leading the variable block size ME research now. A summary of many kinds of ME architecture is in his paper: Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Added after 4 minutes:

I have implement some arhitectures for FPGA, the data flow control is the bigest challange, especially for large vidoe size.
 

    win3y

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win3y

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Re: Need some hints about getting pixel data from memory on

nxtech said:
Choose the FPGA you plan to use then look at the users guide for details on how to implement the on board memory.

E
Hi Nxtech and Darui;
I highly appreciate your suggestion so I have voted "helped" for you.
But now I still do not how to construct the module that its output is 8bit binary pixel from memory therefore I need further helps .
Wish you well!
 

thuyet

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HI WIN3Y
first how do you store you data in memory?.block ram on FPGA or you use external ram?and then you will design output module?
why don't you tell clearlt about your program's wrorking maybe i can help you.
good luck!
 

    win3y

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darui

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Maybe, you need to build a addr generator to pump both the Y data of the current pix and reference pix form deferent memories. The addr is composed with base addr and offset addr. The base addr defines the MB position in the pic, and the offset addr scan the Y data in the MB. The different reference addrs are contained in PE array.
I think Sun M.T.'s paper discussed the addr generator clearly.
 

    win3y

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Iouri

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to darui:

What resolution are you getting and what FPGA devices you used for that resolution?
 

win3y

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Re: Need some hints about getting pixel data from memory on

darui said:
Maybe, you need to build a addr generator to pump both the Y data of the current pix and reference pix form deferent memories. The addr is composed with base addr and offset addr. The base addr defines the MB position in the pic, and the offset addr scan the Y data in the MB. The different reference addrs are contained in PE array.
I think Sun M.T.'s paper discussed the addr generator clearly.
Thank you, Darui and Thuyet;
==> Mr.Thuyet: My main module includes:
+ 2 inputs: 32bit for current pixel and reference pixel.
+ Output is SAD between them.
Module function is calculation of SAD that base on PE Array.
==>Darui: Your instructions makes me understand much clear about memory organization but actually I do not know exactly the syntax to manipulate with pixel data on memory, pls show me more detail (if it is inconvenient, pls private message to me).
Thank you so much!
 

darui

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I used the primitive because it can set value for DCT Quant by using margin of the dual port memory. u can also use CoreGenerator but the more files are generated.
The flowing is a module of a dual port RAM i used for vidoe data acqusition. I used 8 BRAM of this kind to reformat BT656 to MB based.

module sv_zsram00(DOA,DOB,ADDRA,ADDRB,CLKA,CLKB,DIA,DIB,ENA,ENB,WEA,WEB);

output [1]DOA; // 32-bit A port data output
output [15]DOB; // 32-bit B port data output
// .DOPA(DOPA), // 4-bit A port parity data output
// .DOPB(DOPB), // 4-bit B port parity data output
input [12]ADDRA; // 15-bit A port address input
input [9]ADDRB; // 15-bit B port address input
// .CASCADEINA(CASCADEINA), // 1-bit cascade A input
// .CASCADEINB(CASCADEINB), // 1-bit cascade B input
input CLKA; // 1-bit A port clock input
input CLKB; // 1-bit B port clock input
input [1]DIA; // 32-bit A port data input
input [15]DIB; // 32-bit B port data input
// .DIPA(DIPA), // 4-bit A port parity data input
// .DIPB(DIPB), // 4-bit B port parity data input
input ENA; // 1-bit A port enable input
input ENB; // 1-bit B port enable input
// .REGCEA(REGCEA), // 1-bit A port register enable input
// .REGCEB(REGCEB), // 1-bit B port register enable input
// .SSRA(SSRA), // 1-bit A port set/reset input
// .SSRB(SSRB), // 1-bit B port set/reset input
input WEA; // 4-bit A port write enable input
input WEB; // 4-bit B port write enable input

RAMB16_S2_S18 #(
//.DOA_REG(1), // Optional output registers on A port (0 or 1)
//.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
// .INVERT_CLK_DOA_REG("FALSE"), // Invert clock on A port output registers ("TRUE" or "FALSE")
// .INVERT_CLK_DOB_REG("FALSE"), // Invert clock on A port output registers ("TRUE" or "FALSE")
// .RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
// .RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
// .READ_WIDTH_A(9), // Valid values are 1, 2, 4, 9, 18, or 36
// .READ_WIDTH_B(18), // Valid values are 1, 2, 4, 9, 18, or 36
// .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE"
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("READ_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_MODE_B("READ_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
// .WRITE_WIDTH_A(9), // Valid values are 1, 2, 4, 9, 18, or 36
// .WRITE_WIDTH_B(18), // Valid values are 1, 2, 4, 9, 18, or 36

// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h8ffa49fae1e52c4b8f8f8f8f4be52c4b8f8f8f462be14b4b8f8f4949f1fae8fa),
.INIT_01(256'h8f8f49fb493bfbe58f8ffbfb493bfb13fa8f8f492c2c2c13fa498f462c2c2c13),
.INIT_02(256'h96a5bdc9c4b18f798995a4afb29f8672717b8795938373616069737e7d726559),
.INIT_03(256'h4b61819b9c886b58607591acab9577617d9075c0bda5826b90a2bacfc9af8d77),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h05a805a805a805a805a805a805a805a800000000000000000000000000000000),

// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAMB16_inst (
// .CASCADEOUTA(CASCADEOUTA), // 1-bit cascade output
// .CASCADEOUTB(CASCADEOUTB), // 1-bit cascade output
.DOA(DOA), // 32-bit A port data output
.DOB(DOB), // 32-bit B port data output
// .DOPA(DOPA), // 4-bit A port parity data output
// .DOPB(DOPB), // 4-bit B port parity data output
.ADDRA(ADDRA), // 15-bit A port address input
.ADDRB(ADDRB), // 15-bit B port address input
// .CASCADEINA(CASCADEINA), // 1-bit cascade A input
// .CASCADEINB(CASCADEINB), // 1-bit cascade B input
.CLKA(CLKA), // 1-bit A port clock input
.CLKB(CLKB), // 1-bit B port clock input
.DIA(DIA), // 32-bit A port data input
.DIB(DIB), // 32-bit B port data input
// .DIPA(DIPA), // 4-bit A port parity data input
// .DIPB(DIPB), // 4-bit B port parity data input
.ENA(ENA), // 1-bit A port enable input
.ENB(ENB), // 1-bit B port enable input
// .REGCEA(1'b0), // 1-bit A port register enable input
// .REGCEB(1'b0), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(WEA), // 4-bit A port write enable input
.WEB(WEB) // 4-bit B port write enable input
);

endmodule

Added after 3 minutes:

the following is a simple testbench

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:57:46 11/22/2005
// Design Name: sv_sram_dct_primitive
// Module Name: sim_sram.v
// Project Name: SV_TEST1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sv_sram_dct_primitive
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module sim_sram_v;

// Inputs
reg [12:0] ADDRA;
reg [9:0] ADDRB;
reg CLKA;
reg CLKB;
reg [1:0] DIA;
reg [9:0] DIB;
reg ENA;
reg ENB;
reg WEA;
reg WEB;

// Outputs
wire [1:0] DOA;
wire [15:0] DOB;
wire [3:0] off_portb;
assign off_portb=4'b1111;

// Instantiate the Unit Under Test (UUT)
//sv_sram_dct_primitive uut (
sv_zsram00 uut (
.DOA(DOA),
.DOB(DOB),
.ADDRA(ADDRA),
.ADDRB(ADDRB[9:0]),//{off_portb[3:0],ADDRB[5:0]}),
.CLKA(CLKA),
.CLKB(CLKB),
.DIA(DIA),
.DIB(DIB),
.ENA(ENA),
.ENB(ENB),
.WEA(WEA),
.WEB(WEB)
);

wire [47:0] p_out;
wire [15:0] data_doa;
// assign data_doa={DOA[7:7],DOA[7:7],DOA[7:7],DOA[7:7],DOA[7:7],DOA[7:7],DOA[7:7],DOA[7:7],DOA[7:0]};
reg rst;
/* DspSet_dct uut_dct (
.clk(CLKA),
.cs(ADDRA[2:0]),
.rst(rst),
.data_doa(data_doa),
.p_out(p_out)
);*/

reg [7:0] i;

initial begin
// Initialize Inputs
ADDRA = 0;
ADDRB = 0;
CLKA = 1;
CLKB = 1;
DIA = 0;
DIB = 0;
ENA = 1;
ENB = 1;
WEA = 0;
WEB = 1;
rst=0;
#103 rst=1;

// Wait 100 ns for global reset to finish
#100;
ENA=1;
ENB=1;
for( i=0;i<64;i=i+1)
begin
#20
ADDRA=i;
ADDRB=i;
end
#100;
$stop;

// Add stimulus here

end

always #10 CLKA=~CLKA;
always #10 CLKB=~CLKB;

endmodule
 

    win3y

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win3y

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Re: Need some hints about getting pixel data from memory on

WOW, It is really wonderful! I do it now, thank you so much!
If I have some questions, pls help me again :D
Have nice day!
 

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