yuly330
Newbie level 1
Hello to all, I'm new here and I have some problems with the understanding of a piece of VHDL code and I will be very happy if someone could help me to understand it. I had found a tutorial on internet about how to create a VHDL PWM audio generator, and I don't understand this piece of code:
From this project:View attachment PWMDriver.txtView attachment PWMAudio.txt
Thank you in advance!
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 process(CLK100MHZ) begin if rising_edge(CLK100MHZ) then if sine_count = sine_freq then lut_addr <= lut_addr + 1; sine_count <= (others => '0'); else sine_count <= sine_count + 1; end if; end if; end process;
From this project:View attachment PWMDriver.txtView attachment PWMAudio.txt
Thank you in advance!
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