Need some help-PwmAudio in VHDL

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yuly330

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Hello to all, I'm new here and I have some problems with the understanding of a piece of VHDL code and I will be very happy if someone could help me to understand it. I had found a tutorial on internet about how to create a VHDL PWM audio generator, and I don't understand this piece of code:
Code VHDL - [expand]
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process(CLK100MHZ)
begin
    if rising_edge(CLK100MHZ) then
        if sine_count = sine_freq then
            lut_addr <= lut_addr + 1;
            sine_count <= (others => '0');
        else
            sine_count <= sine_count + 1;
        end if;
    end if;
end process;

From this project:View attachment PWMDriver.txtView attachment PWMAudio.txt
Thank you in advance!
 
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This is simply incrementing a counter from 0 to "sine _freq". When it reaches "sine_freq" it increments "lut_addr" and resets the counter and starts over again.

My guess is that it iw using "lut_addr" to index data in a lookup (sine) table.
 
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