Need some good material on DDR DRAM to design DDR2 memory controller

[siddharthakala]

Hi,

I need to design a DDR2 memory controller for Atlys board with Spartan-6 FPGA. I was wondering if someone could suggest some good learning material to understanding the working of DRAMs and memory controllers.

I am not looking for memory controller codes but for their working so I could design and implement the controller myself.

Thanks

 

[syedshan]

Dear

I think following links will be helpful

https://www.anandtech.com/show/3851...w-about-sdram-memory-but-were-afraid-to-ask/2

https://www.ccs.neu.edu/course/com3200/parent/NOTES/DDR.html

Best you go to JEDEC website and download the specification for it

Well, Xilinx has its IP for DDR controller, you can make it using Core Gen.
It is called Memory Interface Generator (MIG). through it you can design interface for different type of memories.
Find MIG or memory interface user guide or tutorial. You dont have to design it. Just use it...

And by the way if you understand its implementation well. Share as well.. since I am also to work on it...

 

[siddharthakala]

Thanks a lot Shan. This seems quite helpful.

I know about Xilinx'x MIG, but actually, I want to design my own controller, maybe just a very simple one, rather than using an IP core.

Will share it as soon as I get done with it.