Re: pipeline ADC design
"If I want to design a 12bit, 65 or 80MHz pipeline ADC, how can I get the various modules' parameters, such as the sample resolution, OTA gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my aim? Thanks very much.
carl "
Hi
As your target 12bit, 65-80MHz pipeline ADC..so at first decide what will be the specifications of sub blocks ( i.e opamp, comparator, S&H, MDAC, voltage reference etc.)
error tolerance of the 1st stage 1/4096 v (if your FSV = 1V) for that reason you require more than 80dB open loop gain.
here i am attaching one pdf file for your ready reference.
bye...