Need of Netlist in verilog

[Manuv16589]

Use of Netlist in verilog

Hi,
While compiling a code in verilog i noticed a file called netlist. What is this netlist? If i am right so it provide the information about interconnections of RTL code. What is the use of it?

 

[FvM]

Compiled netlist is not RTL, it's representing synthesized gate level logic according to the available hardware resources. It can be used for a gate level simulations or verification purposes.