The logic in post #1 has some issues.
The phase between pos_count and neg_count is undetermined. Depending on the reset timing either pos_count or neg_count will increment first, giving different clk_out waveforms. It's even possible that reset release is coinciding with a clock edge, resulting in unexpected counter values.
You may do this:
1. Use a reset synchronizer (if not already present)
2. Use only one counter, derive the neg_edge action from pos_edge controlled signals.
Be aware that generated clocks are likely to cause timing issues if they are combined with the original clock in downstream logic.