I am designing a SOC for 32K * 8 bit sram with two level decoder hence i need to know whether we have anything for the n bit decoder or need to design the smaller decoder and combining them to get a bigger decoder. kindly help me out. thanks in advance
The decoder should be based on the SRAM interface(s). Since we can't guess which SRAM IP you are using, no one can produce a decoder for you. Either way, it looks like you have an address with N bits, which you wish to split into two ranges, lower range going to SRAM A and higher range going to SRAM B. If this is what you want, this is trivial.
yes you are pretty much correct i am doing the same, the thing i need to know is i have got 512 addresses to decode using 9 bits for each sub modules, so do i have to go for a 9 bit decoding logic fully or can i do it in general for n bits.
If I understand correctly..
32k needs 15 address lines, 512 needs 9 adress lines
So you have 64 blocks of 512 bytes of RAM.
You need to decode 15- 9 = 6 lines... giving 64 "select" lines...one for each block.
Thank you for your response, you have seen it correctly my question is that i have to write the code for the entire decoding logic or can we design using n bit design in general.
Thanks in advance
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Klaus
Thank you for your response, you have seen it correctly my question is that i have to write the code for the entire decoding logic or can we design using n bit design in general.