Need low noise JFET with high pinch off voltage

[Schmocki]

Hi,

as the dynamic range of a variable attenuator built with a JFET is dependent on the pinch off voltage (I know about the increasability by feeding back part of the drain voltage to the gate) I am looking for a JFET with a pinch off voltage being as high as possible (10V and up are very welcome, 6.5V should be something I can start with.
Specification does not have to be 10V minimum as I could buy a few more devices and select for high Vp.

Of course it should also have low noise (especially flicker noise) as I would not want to loose the dynamic range I have won by being able to process higher levels to the fact that I can not use the lower levels anymore because of too high a noise voltage.

RdsOn at Vgs=0V should be around 25 to 100 ohms, while higher values are not that critical as I could parallel a few devices.
JFETs with lower RdsOn might also work if Vp is high enough.

Many thanks in advance for any suggestions.
Schmocki

 

[keith1200rs]

The obvious place to look is Vishay, but I guess you have looked there. Interfet do some unusual devices, so they would be worth a look.

Keith

 

[FvM]

The obvious place to look is Vishay.

It isn't since Vishay silently left the JFET market. Interfet is providing a second source for most former Siliconix/Vishay types, except for some dual types, and those Siliconix types that have been previously discarded by Vishay.

From those, the former Siliconix process NC (apparently similar to Interfet NJ132) with types as 2N4391, J111 would be my first choice. Selection of types with Vp > 6.5 V would be necessary though.

 

[keith1200rs]

I didn't realise Vishay weren't still making the old Siliconix ones. I have only used Interfet low noise JFETs over the last few years.

Keith.

 

[Schmocki]

Hi,

thank you for your quick answers!
The 2N4391 and J111 are nice regarding the high pinch off voltage but unfortunately their RdsOn are much too low (30 Ohms for VgsOff of 3V, so maybe 10 ohms for devices with VgsOff above 9V).
I would have to bias the gate with a quite high negative voltage to get into the desired resistance range which would take away the advantge of the higher pinch off voltage.

A 2N4391 with one half of the gate width selected to Vgs>9V would be great.

Does anyone know who else in addition to Interfet is still making JFET?

Regards,
Schmocki

 

[FvM]

I would have to bias the gate with a quite high negative voltage to get into the desired resistance range which would take away the advantge of the higher pinch off voltage.

I don't exactly understand what's the issue in this regard. But you should know what you're trying to achieve.

JFETs are e.g. made by Fairchildsemi and NXP. They have industry standard types, and in case of NXP, some devices with optimized RF properties. As far as I see, none is falling in the requested category. I think, you have to decide if either Up or rdson is more important.

By the way, the P-JFET J174 would better fit both criteria.

 

[Schmocki]

The issue is dynamic range.

Lower Vp limits the possible signal voltage level due to nonlinearities.
Lower RdsOn limits the possible signal voltage level because of the needed impedance matching (maximum available power is limited).
The noise voltage of the next stage is fixed, so the lower output impedance in case of a low ohmic JFET does not help here.

The J174 would fit exactly for the Vp and RdsOn requirements but unfortunately its noise voltage is too high to make it useable.
But thank you for the suggestion, I appreciate your help very much.

Schmocki

 

[FvM]

My thought was, that you can always utilize the FET up to the pinch-off voltage, even if the rdson is lower than optimal. But apart from a less than optimal control characteristic, you need up to -2*Vp when using a gate voltage divider, possibly involving a step-up converter for the control supply.

Generally, it's obvious that FET variable resistor circuits never played an important role in analog design. They have been used at times for VCAs in professional audio, but have been mostly replaced by linearized gm multipliers that gave better performance and above all, reproducable characteristics. Now these specialized devices are gone, too, because everything is done in the digital domain.

 

[Schmocki]

With real devices you have to stay clear quite a bit from Vp with the gate voltage, as close to Vp the characteristic deviates from square behaviour and so the linearisation with the gate voltage divider does not work work very good anymore.
The J174 is very good with respect to this as it has very low deviation from square law up to Vp but as already mentioned before it unfortunately is quite noisy :-(

So if I have to bias the gate to -2/3 of Vp to get my "on" resistance there is not much room left for resistance control before I enter the non-square region and become nonlinear.

 

[Schmocki]

Hi,

I came across the BF246C which seems to have very high Vp.

**broken link removed**

One strange thing is that if I calculate gm @ IDss from IDss and Vp I get roughly 40mS for all three bins (A, B and C).
Usually gm at IDss increases with higher IDSS and gm of the higher IDss bins comes close to gm of the lower IDss bins when biased to the same drain current.

In the same PDF above there is also the BF256 which also shows a strange behaviour in this respect. At the end of the PDF you can see the graphs for gm vs. ID and here the curves for the three bins differ very much while with other JFETs I know the curves almost overlap until the curves for the lower IDss bins end at the point where ID is equal to IDss.

Does anyone know a technical explanation to this? Are these JFETs processed differently from other ones and hence the IDss (and/or Vp) variations result from variations in different parameters than in other FETs?

Schmocki

 

[erikl]

Are these JFETs processed differently from other ones ...?

Don't think so. At least Fairchild's BF246B dataSheet says it is equivalent to the J111 .

 

[FvM]

FET equations based on a square law characteristics are always a simplification, but they are known to be less valid for high gm types. For BF246, gm@Vgs=0 is more or less a virtual parameter, because it can't be utilized for amplifiers. But it's specified in some datasheets as 25 mS (mmmho) typical. In Interfet's NJ132 process datasheet, the transconductance is approaching a constant value slightly above 30 mS for higher Vp.

 

[Schmocki]

Interesting point. But why does RdsOn go on sinking with increasing VgsOff while gm almost stays the same?

Also IDSS looks linearly dependent on VgsOff in the process datasheet which would explain the fixed gm but not the falling RdsOn.

If these data are true (which should be as the manufacturers would not provide us with false datasheets) there must be a technical explanation for this effect.

Schmocki

Edit:

Could this just be a high source contact resistance?

 

[FvM]

My technical explanation is simple: The assumptions of the square law aren't valid.

 

[Schmocki]

Hi,

here on page 5 is a nice explanation of Rs corrupting the square law.

So if I want the linearisation network to work correctly I have to stay away from near the Vp and also avoid the region where Rs is not negligible anymore.

Seems I am going to order a lot of samples and invest some major time in curve tracing and spice parameter extrahation...

Unfortunately most manufacturers do not provide JFET spice data, and if they do, there is doubt on their accuracy.

I often see Rs and Rd just set to 1 ohms default value...

Schmocki

 

[FvM]

I also expect, that adding terminal resistance can improve the accuracy of the basic JFET model. But it's still a simple one, and won't model all real world effects. I don't however understand your point about the linearization network. Symmetrical terminal resistances won't affect the operation of the standard linearization, I think. By the way, did you actually observe higher non-linearity near Vp or ist it just an assumption.

 

[Schmocki]

Hi,

**broken link removed**

Second page, upper left figure.

This is regarding LDMOS but that behaviour near Vp should be similar in JFETs.

These figures show deviation from square law quite dramatically:



gfs should be a straight upwarts heading line from Vp to the left with some knee where it begins to limit due to Rs. But the knee is close to Vp and after the knee the line is still upwards pointing and not limited to max gfs as would be with a knee due to Rs.

Schmocki

 

[FvM]

You didn't tell for wich part the shown characteristics apply. It seems like they are for a Siliconix/Vishay NZF chip (e.g. E300, U312 devices).

 

[Schmocki]

J202

The J174 has much better square law characteristics (seems all the P channel types have) but is much noisier.

Interestingly PNP transistors have lower noise than NPN, P-doped schottky diodes have lower noise than N-doped but P-JFETs seem to have higher noise than N-JFETs.