need information on How PLL Locks the clock comming on bus

[vinod_g]

PLL LOCK

Hi

Can any one give the information on How PLL Locks the clock comming on the bus?

 

[ring0]

Re: PLL LOCK

It measures phase difference between the incoming clock and the internally generated clock, and controls the internally generated clock frequency trying to make this phase difference zero.

See https://en.wikipedia.org/wiki/PLL[/url]