Need info about latch up failure

[jason_class]

Dear All

I need some help to understand more about latch up failure.
Usually, latch up failure happens are due to improper layout of design OR due to process issue?

I heard that often latch up failure happens in IO mos. What are they for? Why it is often the case latch up happens at IO mos? Is the W/L bigger than normal logic mos or some other reason?

If anyone has any good reference on this topic, kindly share with me.

Thank you for your help.

best rgds
Jason

 

[road_0506]

Re: Latch up

Hello!
Try to read the attachment...
Hope it will help...
Regards

 

[vbhupendra]

Re: Latch up

as IO transitors are directly connected to pins so there is high possibility of change of voltage levels at those pins; sufficient to trigger latchup.

 

[manissri]

Re: Latch up

read the book of kang which will be very helpful for latchup.

 

[qiushidaren]

Re: Latch up

Hello!
Try to read the attachment...
Hope it will help...
Regards

Thanks for your doc, it really helps, I have downed it!

 

[jason_class]

Re: Latch up

Dear All


To All who have commented and given the document, I really appreciate your help!
Let me digest the material and shall be back for further discussion.

By the way, if anyone has any experience in process induced latch up , kindly share with me your opinion.

Thank you All


best rgds
Jason

 

[sengyee88]

Re: Latch up

I think purpose of IO mos is to do ESD protection. It uses its parasitic diode to drain away ESD current. This parasitic diode is also forming the latch up transistors and if it doesn't take good care, it will induce latch up.

ESD protection and latch up is a trade off if you are using MOS. The better ESD protection the MOS can give, the easier latch up will happen to the MOS.

 

[jason_class]

Re: Latch up

Dear Seng Yee & All

Thanks a lot everyone. Your advice are very useful. I am quite agree with what Seng Yee mentioned here and that leads me to some books to understand better. I indeed find some relation between ESD and IO device. Currently still reading for better digestion.....

Thank you !

best rgds
Cheang Long

 

[YESH_23]

Latch up

its purely dependent on the layout that we are going to lay.

 

[its_thepip]

Re: Latch up

Latch up means the SCR trigerring of mos amplifier.
it depends upon the layout u chose.

Added after 52 minutes:

latch up means shortciruiting

Added after 1 minutes:

HI