Seems to me if your 20 Khz was developed by a DDS, use another DDS and simply
offset the phase accumulator to get necessary delay/offset. So second DDS becomes
the 20 Khz master....
This would have to constrain 20 Khz to be deterministic.
So scheme requires a PLL to generate a high freq source clk for the DDS's to generate accurately
the 20 Khz. But the PLL adds latency, step response issues, etcc. This chip has multiple DDS's you can use. As well as a lot of other analog and logic and ARM and resources.
Alternatively, I am not a Verilog expert, but seems since you can afford 1
pulse delay, a pulse measurement could be made and then applied to
network to create the offset new master 20 Khz....I will let the Verilog experts
here comment on this.
What is your drop dead latency, the 1 pulse you mention ? What is the resolution
accuracy you need in the offset waveform ?
Regards, Dana.