Consider, that an interrupt input has to be asserted at least one CPU clock long, possibly longer depending on the processor family.
In case, that the processor, or what ever has to be interrupted is reading the GPIO states on interrupt, you would want that the next compare is done with the bit vector it has read, at least if the individual bits are expected to change at arbitrary times. To implement this feature, you need an acknowledge pulse to trigger state latching. The automatic latching is of no use for it.