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Need Helps for designing 3T DRAM!!!

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ferrarimaker

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Q:Design a 3-transistor CMOS DRAM cell. Show that the read and write operation is functionally correct, capable of operating of at least 100 MHz, and consuming very minimal power.
(input rise time (10%-90%) and fall time (90%-10%) should be at most 1 ns.)
(0.35micron technology)

the information should be available in the cell within 2 ns, i.e propagation delay = 2 ns, and it should be available for another 10 ns (the hold time = 10ns)

=> for write 1 and read 1 operation, what's the steps to determine the capacitance value and (W/L) ratio of the NMOS?

=> please provide the necessary equations

(the 3T DRAM circuit diagram is attached with this message)

thanks
 

omsi

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refer to CMOS memory design by Tegeze p Hazrathi
 

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