Need help with this VHDL code. Integer output showing as binary in Isim.

[navienavnav]

I wrote the following code the purpose of which is to count the number of 1's in an 8-bit binary number....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity count_ones_nav is

port ( inp : in std_logic_vector(7 downto 0);
       outp : out integer range 0 to 8);
end count_ones_nav;

architecture Behavioral of count_ones_nav is

begin

process(inp)
variable c : integer range 0 to 8;
begin

c := 0;
for x in 0 to 7 loop
 if inp(x)='1' then
    c:=c+1;
 end if;
end loop;

outp<=c;
end process;

end Behavioral;

It is showing the correct count in ISim, but it is showing it as binary. For example, if the number of 1's are 6, then it is showing 110 after simulation in the ISim. Is this the correct way because ISim only shows values in binary (because of the waveform and being a digital output) or am I doing something wrong?

 

[TrickyDicky]

the eventual design will have outp as a binary number, as everything in an fpga is binary. I assume you're doing a post place and route simulation, rather than an RTL simulation (because that should show an integer).

 

[dftrtl]

RTL simulation shows integer value and GLS simulation shows binary value.

 

[navienavnav]

Ah okay, thanks.