Need help with small ALU design problem

[Spiz]

Hello!

I'm sorry if I'm posting a question with a rather simple solution, but I have looked everywhere and I couldn't find a solution to my problem.

We had to design a 4-bit ALU module (without usage of process block) and I guess I managed to get most of it right.
However whenever I try to synthetize my module, I get following error message:

Width mismatch, location has width 4, value 8

and it leads me to the line with multiplication, which basically means I don't know how to make Z width have value 8 while my ALU is multiplying and have value 4 when performing other operations.

I am hoping someone might have a solution to that.

Below is my ALU code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
entity ALU is

	generic (
		C_data_width: integer := 4
	);
   port
   (
      A, B: in std_logic_vector((C_data_width - 1) downto 0);
      ALUOp: in std_logic_vector(2 downto 0);
      Z: out std_logic_vector((C_data_width - 1) downto 0)
   );
end ALU;

 
architecture beh of ALU is
    signal R_A, R_B: std_logic_vector((C_data_width - 1) downto 0);
    signal R_ALUOp: std_logic_vector(2 downto 0);
    signal R_Z: std_logic_vector((C_data_width - 1) downto 0);
	
begin
		Z <=
			A * B when (ALUOp = "000") else    --MUL
			A + B when (ALUOp = "001") else    --ADD
			A nor B when (ALUOp = "010") else  --NOR
			A xor B when (ALUOp = "011") else  --XOR
			A and B when (ALUOp = "100") else  --AND
			A - B when (ALUOp = "101") else    --SUB
			shr(A,B) when (ALUOp = "110") else --SLR
			A or B when (ALUOp = "111");   	   --OR
	end beh;

 

[Taner]

Multiplication (A * B) can return 8-bit value, and you should define the Z like 8-bit vector.

 

[Spiz]

I tried that already, if I define Z as 8-bit vector, it gives me similar error, but this time for other operations, like addition, where it says Z is 8-bit, while it expects it to be 4-bit sized.

 

[TrickyDicky]

You should never use the packages numeric_std and std_logic_arith in the same file. You should stick with numeric_std because it is the IEEE standard package.

But like Taner said, A*B gives an 2*C_data_width result.
Technically, to avoid overflow, A+B and A-B have a carry bit too.

 

[Spiz]

Yeah, now I tried again making Z 2*C_data_width and basically the result is the same, except that error says "Width mismatch, location has width 8, value 4" and it points at code line with addition formula.
Still thanks a lot guys for even trying to help me!

 

[153rd]

What you could try(doing it is a bit hard cumbersome) is making components of 2 bit adders with a carry bt, then link these together. You can then use that component as a multiplier.
It tackles the carry/overflow problem, but again, is a bit of a hard workaround

 

[Spiz]

Thank you, I think that would work, but I don't think we're allowed to make that for this practice, our professor said our ALU basically should look like as if it was a multiplexer of sort. Also in instructions we were given, it says I specifically have to use generic parameter so I can edit signal widths and even make our ALU for example 32-bit if needed. So I'm not sure how that would that be possible if I made ALU out of 2 bit adders with carry bit.

 

[TrickyDicky]

THere are other ways to build multiplexors.

But you could always pad all the answers with '0's. For example:

z : out std_logic_vector(7 downto 0);

z <= A * B when opcode = "000" else
     "000" & ( ('0'&A) + ('0' & B) ) when opcode = "001" else --no overflow
--etc.

 

[Spiz]

Thank you so much for this!
Padding the oter answers with '0' worked