library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity ALU is
generic (
C_data_width: integer := 4
);
port
(
A, B: in std_logic_vector((C_data_width - 1) downto 0);
ALUOp: in std_logic_vector(2 downto 0);
Z: out std_logic_vector((C_data_width - 1) downto 0)
);
end ALU;
architecture beh of ALU is
signal R_A, R_B: std_logic_vector((C_data_width - 1) downto 0);
signal R_ALUOp: std_logic_vector(2 downto 0);
signal R_Z: std_logic_vector((C_data_width - 1) downto 0);
begin
Z <=
A * B when (ALUOp = "000") else --MUL
A + B when (ALUOp = "001") else --ADD
A nor B when (ALUOp = "010") else --NOR
A xor B when (ALUOp = "011") else --XOR
A and B when (ALUOp = "100") else --AND
A - B when (ALUOp = "101") else --SUB
shr(A,B) when (ALUOp = "110") else --SLR
A or B when (ALUOp = "111"); --OR
end beh;