need help with simple fibobazzi code

[lior2000]

hello
i'm new with verilog and i want to design fobonazzi code that work recorsively.

i try to use this code at modelsim:



module fib(number, value);
input number;
output value;
wire number;
reg value;


reg v1;
reg v2;

if(number < 2)
value = number;
else
begin
fib f1 (number-1,v1);
fib f2 (number-2,v2);
value = (v1+v2);
end
endmodule

but it can't compile with this errores:
# ** Error: I:/project/fib/fib.v(12): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER
# ** Error: I:/project/fib/fib.v(17): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER

how to fix it? it's very importent to me and little urge.
i don't know enough about verilog and i'm trying to study so pls explain me as much as you can.

lior

 

[ads_ee]

you need the assign keyword.

---

Code Verilog - [expand]
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assign value = number;
  assign value = (v1+v2);

---

But I doubt this code will synthesize, I haven't seen recursion used for synthesizable logic in verilog (or I've never found a use case for it).

Verilog tasks can use recursion if they are made automatic, but then tasks are more of a programming structure used in testbenches.

 

[lior2000]

you need the assign keyword.

---

Code Verilog - [expand]
1
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assign value = number;
  assign value = (v1+v2);

---

But I doubt this code will synthesize, I haven't seen recursion used for synthesizable logic in verilog (or I've never found a use case for it).

Verilog tasks can use recursion if they are made automatic, but then tasks are more of a programming structure used in testbenches.

ithought about it but it didn't help. i tried to compile it now:

module fib(number, value);
input number;
output value;
wire number;
reg value;


reg v1;
reg v2;

if(number < 2)
assign value = number;
else
begin
fib f1 (number-1,v1);
fib f2 (number-2,v2);
assign value = (v1+v2);
end
endmodule


and got the errore:

# ** Error: I:/project/fib/fib.v(11): The generate if condition must be a constant expression.
# ** Error: I:/project/fib/fib.v(12): Register is illegal in left-hand side of continuous assignment
# ** Error: I:/project/fib/fib.v(17): Register is illegal in left-hand side of continuous assignment

 

[ads_ee]

ithought about it but it didn't help. i tried to compile it now:

---

Code Verilog - [expand]
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module fib(number, value);
  input number;
  output value;
  wire number;
  reg value;
   
 
reg v1;
reg v2;
   
   if(number < 2) 
     assign value = number;
 else
     begin
      fib f1 (number-1,v1);
      fib f2 (number-2,v2);
     assign  value = (v1+v2);
    end
    endmodule

---

and got the errore:

# ** Error: I:/project/fib/fib.v(11): The generate if condition must be a constant expression.
# ** Error: I:/project/fib/fib.v(12): Register is illegal in left-hand side of continuous assignment
# ** Error: I:/project/fib/fib.v(17): Register is illegal in left-hand side of continuous assignment

value should be a wire not a reg type, didn't notice that earlier.

As I said this code would likely not synthesize. Based on the following:

# ** Error: I:/project/fib/fib.v(11): The generate if condition must be a constant expression.

It probably won't work as written. You can't just have arbitrary code produced based on a variable (input port number). This isn't C.

I would rewrite this using a parameter to set the number and a generate & for structures to produce the logic.

 

[sureshaa]

Hi lior,

Like ads_ee said, I dont think so i can be synthesisable. hereby I have attached a code for fib' series generation.I hope it will useful for you.
module FibGen(clk, rst, enb, out);

input clk, rst, enb;
output [16:0] out;
reg [16:0] out;

// states
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;

// used to initialize registers
parameter Zero_16 = 16'b0000000000000000;
parameter One_16 = 16'b0000000000000001;

reg [16:0] reg_0 = Zero_16;
reg [16:0] reg_1 = One_16;
reg [16:0] fib = Zero_16;

reg [2:0] State;

always @ (posedge rst or posedge clk)
begin
if( rst == 1 )
begin
reg_0 = Zero_16;
reg_1 = One_16;
fib = Zero_16;

State <= S0;
out <= Zero_16;
end
else
begin
case( State )
S0:
begin
// determine next state
if( enb == 1 )
State <= S1;
else
State <= S0;

// assign output value
out <= reg_0;
fib <= reg_0;
end

S1:
begin
// determine next state
if( enb == 1 )
State <= S2;
else
State <= S1;

// assign output value
out <= reg_1;
fib <= reg_1;

end

S2:
begin
// determine next state
if( enb == 1 )
State <= S2;
else
State <= S3;

// update values and assign output value
out <= reg_0 + reg_1;
fib <= reg_0 + reg_1;
reg_0 <= reg_1;
reg_1 <= reg_0 + reg_1;
end

S3:
begin
// determine next state
if( enb == 1 )
State <= S2;
else
State <= S3;

// assign output value
out <= fib;
end
endcase
end
end
endmodule