Need help with my 4-bit Fibonacci LFSR!!

[owenljn]

First thanks for clicking in my thread
I implemented my design for a 4-bit Fibonacci LFSR, but when I try to compile it, it says warning:No clocks defined in design, it compiles successfully but when I test it on DE2 board, it doesn't work, so here's my verilog code:

module LFSR4bit (KEY, LEDG, HEX0);
input [1:0] KEY;
output [3:0] LEDG;
output [0:6] HEX0;

wire [3:0] Q;
wire D;
assign D = Q[2]^Q[3];
Flip_Flop F0 (KEY[0], D, Q[0]);
Flip_Flop F1 (KEY[0], Q[0], Q[1]);
Flip_Flop F2 (KEY[0], Q[1], Q[2]);
Flip_Flop F3 (KEY[0], Q[2], Q[3]);

assign LEDG = Q;
QtoHEX Q0 (Q, HEX0);
endmodule

module Flip_Flop (Clk, D, Q);
input Clk, D;
output Q;

wire Qm;
Dlatch D0 (~Clk, D, Qm);
Dlatch D1 (Clk, Qm, Q);
endmodule

module Dlatch (Clk, D, Q);
input Clk, D;
output Q;

wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
assign S = D;
assign R = ~D;
assign S_g = S & Clk;
assign R_g = R & Clk;
assign Qa = ~(R_g | Qb);
assign Qb = ~(S_g | Qa);
assign Q = Qa;

endmodule

module QtoHEX (Q, HEX);
input [3:0] Q;
output reg [0:6] HEX;

always begin
case (Q)
0:HEX=7'b0000001;
1:HEX=7'b1001111;
2:HEX=7'b0010010;
3:HEX=7'b0000110;
4:HEX=7'b1001100;
5:HEX=7'b0100100;
6:HEX=7'b0100000;
7:HEX=7'b0001111;
8:HEX=7'b0000000;
9:HEX=7'b0001100;
10:HEX=7'b0001000;
11:HEX=7'b1100000;
12:HEX=7'b0110001;
13:HEX=7'b1000010;
14:HEX=7'b0110000;
15:HEX=7'b0111000;
endcase
end
endmodule

Here's the lab question:
A linear feedback shift register (LFSR) produces a sequence of pseudorandom numbers { at each new clock
cycle a new pseudorandom number is generated using the previous state of the circuit.
The initial value of the LFSR is called the seed; as the LFSR is deterministic, the sequence of values that
the circuit generates will be based on its seed. There are a number of dierent types of LFSRs; one is the 4-bit
Fibonacci LFSR1
:
Figure 2: A four-bit Fibonacci LFSR. Note that if you use a seed of 0000, the LFSR will never change state! An
animated example of this circuit in action is available at https://en.wikipedia.org/wiki/File:LFSR-F4.GIF
PRELAB TODO: Write Verilog code for a 4-bit Fibonacci LFSR. Use KEY0 for the clock, and display
the current number using a 7-segment display. (Hint: get the LFSR working with LED outputs before switching
it to the 7-segment display!)

 

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What are they trying to teach engineering students!? So many of the students learning Verilog seem to use antiquated syntax and everything is built up of low level gates and master-slave flip flop designs. :-(
I saw simple examples like this in the various Verilog books I own when I picked up Verilog to do my work, but I've never seen anyone actually use this type of coding to implement anything.


This could easily be written in 1 line of behavioral code:

... module stuff, ports etc.
reg [3:0] fib_lfsr = 4'b0001;

// this implements the given picture.
always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[2:0], fib_lfsr[3] ^ fib_lfsr[2]};

...whatever else you want to do...

 

[owenljn]

What are they trying to teach engineering students!? So many of the students learning Verilog seem to use antiquated syntax and everything is built up of low level gates and master-slave flip flop designs. :-(
I saw simple examples like this in the various Verilog books I own when I picked up Verilog to do my work, but I've never seen anyone actually use this type of coding to implement anything.

This could easily be written in 1 line of behavioral code:

... module stuff, ports etc.
reg [3:0] fib_lfsr = 4'b0001;

// this implements the given picture.
always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[2:0], fib_lfsr[3] ^ fib_lfsr[2]};

...whatever else you want to do...

Thanks for your reply, I'll check this right now, btw I'm not engineering student and I'm totally new to verilog, just started to learn it like two weeks ago

 

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So are you a hobbyist? If so learn Verilog like I did (not in school).

I picked up the book "The Verilog Hardware Desciption Language" by Thomas/Moorby and read it cover to cover. This was back in 1995 so it was the only Verilog book that I could find. Now I have a couple of others and the LRM to refer to. A book on testbench development can be very useful too.

 

[owenljn]

So are you a hobbyist? If so learn Verilog like I did (not in school).

I picked up the book "The Verilog Hardware Desciption Language" by Thomas/Moorby and read it cover to cover. This was back in 1995 so it was the only Verilog book that I could find. Now I have a couple of others and the LRM to refer to. A book on testbench development can be very useful too.

Thanks for suggestions, I'm using a book called "Logic and Computer Design Fundamentals" written by M.Morris Mano and Charles R. Kime, and yeah I'm sort of hobbyist, all those simple small gates were from this book

- - - Updated - - -

What are they trying to teach engineering students!? So many of the students learning Verilog seem to use antiquated syntax and everything is built up of low level gates and master-slave flip flop designs. :-(
I saw simple examples like this in the various Verilog books I own when I picked up Verilog to do my work, but I've never seen anyone actually use this type of coding to implement anything.


This could easily be written in 1 line of behavioral code:

... module stuff, ports etc.
reg [3:0] fib_lfsr = 4'b0001;

// this implements the given picture.
always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[2:0], fib_lfsr[3] ^ fib_lfsr[2]};

...whatever else you want to do...

wait, it still doesn't work, when you give a seed like 0001 to it, then the DE2 board only displays 1, it doesn't change when I press KEY0 as the clock signal, here's the code:

module LFSR4bit (KEY0, LEDG, HEX0);
  input KEY0;
  output [3:0] LEDG;
  output [0:6] HEX0;
  
  reg [3:0] Q = 4'b0001;
  always @ ( posedge KEY0 ) 
    Q <= {Q[2:0], Q[3]^Q[2]};

  assign LEDG = Q;
  QtoHEX Q0 (Q, HEX0);
endmodule

module QtoHEX (Q, HEX);
  input [3:0] Q;
  output reg [0:6] HEX;

  always begin
    case (Q)
      0:HEX=7'b0000001;
      1:HEX=7'b1001111;
      2:HEX=7'b0010010;
      3:HEX=7'b0000110;
      4:HEX=7'b1001100;
      5:HEX=7'b0100100;
      6:HEX=7'b0100000;
      7:HEX=7'b0001111;
      8:HEX=7'b0000000;
      9:HEX=7'b0001100;
      10:HEX=7'b0001000;
      11:HEX=7'b1100000;
      12:HEX=7'b0110001;
      13:HEX=7'b1000010;
      14:HEX=7'b0110000;
      15:HEX=7'b0111000;
    endcase
  end
endmodule

I even tried to change always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[2:0], fib_lfsr[3] ^ fib_lfsr[2]}; to always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[3:0], fib_lfsr[3] ^ fib_lfsr[2]}; but the output is static even if I give clock signal to it

 

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The point of reading a book cover-to-cover is so you'll get to see the entire language and then see that coding with gates is not the way to go.

 

[owenljn]

I don't get that annoying warning anymore but the output signal is static, I can't seem to change it by giving it clock signal

 

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How is KEY generated... please, please, don't tell me it's a non-debounced switch on the board. ;-)

You should use an actual clock for the registers not a signal from some switch. As the "switch" input is probably assigned to a non-clock pin the tools are probably routing the "clock" on general interconnect. So you've probably got some horrendous skew in the clock and are probably "loosing" bits when it tries to shift.

Take a look at your timing report....I hope you entered some timing constraints.


1. I'd first add a clock to the design.
2. debounce the switch using the clock to generate a nice clean enable pulse
3. run the LFSR on the clock and use the enable pulse to clock enable the registers.

 

[owenljn]

How is KEY generated... please, please, don't tell me it's a non-debounced switch on the board. ;-)

You should use an actual clock for the registers not a signal from some switch. As the "switch" input is probably assigned to a non-clock pin the tools are probably routing the "clock" on general interconnect. So you've probably got some horrendous skew in the clock and are probably "loosing" bits when it tries to shift.

Take a look at your timing report....I hope you entered some timing constraints.


1. I'd first add a clock to the design.
2. debounce the switch using the clock to generate a nice clean enable pulse
3. run the LFSR on the clock and use the enable pulse to clock enable the registers.

It's a clock key , here's the "clocks" section under timing analysis
Clock name Type Period Frequency Rise Fall
KEY0 Base 1.000 1000.0 MHz 0.000 0.500

 

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It's a clock key , here's the "clocks" section under timing analysis
Clock name Type Period Frequency Rise Fall
KEY0 Base 1.000 1000.0 MHz 0.000 0.500

Uh? 1000 MHz????

That's 1 GHz....I don't think you're going to find any FPGAs that run that fast.

 

[owenljn]

Uh? 1000 MHz????

That's 1 GHz....I don't think you're going to find any FPGAs that run that fast.

it's a key on DE2 board, when I press it down and release, it bounces up

 

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I was hoping it wasn't some bouncy key...

Like I said use a real clock I'm sure the DE2 has a user clock of some sort probably 50 MHz or 125 MHz or something.

Use the 50 MHz clock to debounce the switch and generate an edge detect pulse, which you can use as your enable to the LSFR registers, which are clocked using that 50 MHz oscillator clock.

 

[owenljn]

I was hoping it wasn't some bouncy key...

Like I said use a real clock I'm sure the DE2 has a user clock of some sort probably 50 MHz or 125 MHz or something.

Use the 50 MHz clock to debounce the switch and generate an edge detect pulse, which you can use as your enable to the LSFR registers, which are clocked using that 50 MHz oscillator clock.

I changed to CLOCK_50 which has 50MHz, but now it doesn't even display the "1" every HEX units are displaying "8" just like it's not working and all the four green lights are on but not flashing

 

[mrflibble]

I guess some testbenching may be in order...

 

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It's probably showing 8 because it's cycling so fast through all counts... you need to add an enable to the shift register. operated by an edge detection pulse from the KEY input.

 

[owenljn]

It's probably showing 8 because it's cycling so fast through all counts... you need to add an enable to the shift register. operated by an edge detection pulse from the KEY input.

I just fixed it by swaping the concatenation parts
So
always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[2:0], fib_lfsr[3] ^ fib_lfsr[2]};

Should be


always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[3] ^ fib_lfsr[2], fib_lfsr[0:2]};

Now it's working perfectly

 

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The following code:

module temp (
  output [3:0]  q,
  input         enable,
  input         clk
);

reg [3:0]   lfsr = 4'b0001;

always @ (posedge clk) begin

  lfsr <= enable ? {lfsr[2:0], ^lfsr[3:2]} : lfsr;

end

assign q = lfsr;

endmodule

produces the following waveform...


As this cycles correctly, I'm not sure why switching the shift direction fixes your design.

 

[owenljn]

The following code:

module temp (
  output [3:0]  q,
  input         enable,
  input         clk
);

reg [3:0]   lfsr = 4'b0001;

always @ (posedge clk) begin

  lfsr <= enable ? {lfsr[2:0], ^lfsr[3:2]} : lfsr;

end

assign q = lfsr;

endmodule

produces the following waveform...
View attachment 86994

As this cycles correctly, I'm not sure why switching the shift direction fixes your design.

ok, here's my working code:

module LFSR4bit (KEY, LEDG, HEX0);
  input [1:0] KEY;
  output [3:0] LEDG;
  output [0:6] HEX0;

  reg [0:3] Q = 4'b0001;

  always @ ( posedge KEY[0] )
    Q <= {Q[3]^Q[2], Q[0:2]};

  assign LEDG = Q;
  QtoHEX Q0 (Q, HEX0);
endmodule

module QtoHEX (Q, HEX);
  input [0:3] Q;
  output reg [0:6] HEX;

  always begin
    case (Q)
      0:HEX=7'b0000001;
      1:HEX=7'b1001111;
      2:HEX=7'b0010010;
      3:HEX=7'b0000110;
      4:HEX=7'b1001100;
      5:HEX=7'b0100100;
      6:HEX=7'b0100000;
      7:HEX=7'b0001111;
      8:HEX=7'b0000000;
      9:HEX=7'b0001100;
      10:HEX=7'b0001000;
      11:HEX=7'b1100000;
      12:HEX=7'b0110001;
      13:HEX=7'b1000010;
      14:HEX=7'b0110000;
      15:HEX=7'b0111000;
    endcase
  end
endmodule

 

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  reg [0:3] Q = 4'b0001;

  always @ ( posedge KEY[0] )
    Q <= {Q[3]^Q[2], Q[0:2]};

I see it was the [0:3] definition of Q that was causing the problem. As you see in the code I posted I defined it as [3:0].