whateva
Newbie level 4
dependent counter
I want to implement a logic in verilog in such a way that for 3 clk cycles the output of logic block selects 1 input of the mux, and for the other 4 clk cycles it selects the other input.
Total 7 clk cycles are needed, i want to keep a track of the cycles so i want to use a counter which increments only when the positive edge of the clock comes, kindly tell me how should i do that??
secondly would the counter be dependent on the data clock or the system clock??
I want to implement a logic in verilog in such a way that for 3 clk cycles the output of logic block selects 1 input of the mux, and for the other 4 clk cycles it selects the other input.
Total 7 clk cycles are needed, i want to keep a track of the cycles so i want to use a counter which increments only when the positive edge of the clock comes, kindly tell me how should i do that??
secondly would the counter be dependent on the data clock or the system clock??