Apr 20, 2006 #1 C cheelgo Member level 5 Joined Nov 23, 2004 Messages 82 Helped 4 Reputation 8 Reaction score 1 Trophy points 1,288 Activity points 488 Hi, I am not that familar verilog simulation models, ------ padlib.v ------ module padlib (...); input ...; output ..; wire ...; ... ... `ifdef cve buf #0.001 (...); `else or #0.001 (...); `endif endmodule Question: if I only wanna force this model use cve part, HOW can I configure, can I use set cve true somebody can help. thanks in advance? Cheelgo
Hi, I am not that familar verilog simulation models, ------ padlib.v ------ module padlib (...); input ...; output ..; wire ...; ... ... `ifdef cve buf #0.001 (...); `else or #0.001 (...); `endif endmodule Question: if I only wanna force this model use cve part, HOW can I configure, can I use set cve true somebody can help. thanks in advance? Cheelgo
Apr 20, 2006 #2 A AlexWan Full Member level 5 Joined Dec 26, 2003 Messages 304 Helped 8 Reputation 16 Reaction score 2 Trophy points 1,298 Activity points 2,692 Any simulator has the optional of "+define+macro...". You can find the detail information of the vcs/ncverilog/ncsim/modelsim/... -help.
Any simulator has the optional of "+define+macro...". You can find the detail information of the vcs/ncverilog/ncsim/modelsim/... -help.
Apr 23, 2006 #3 R RP Newbie level 3 Joined Mar 31, 2006 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,308 Hi, I did not quite understand your question. But if you are trying to configure the verilog module, use compiler primitives like "#define cve". RP,
Hi, I did not quite understand your question. But if you are trying to configure the verilog module, use compiler primitives like "#define cve". RP,