Need help to simulate the verilog code given below

[mondeo007]

WHY?

i worte a verilog code, but i can't stimulate by modelsim because this loop

always
for(i=0;i<32;i=i+1)
begin
for(j=0;j<32;j=j+1)
begin
tempreg=regout[j];
tempgroup[j]=tempreg;
end
g=tempgroup;
end

it never stop at second for loop

does anyone know why???
thank so much

 

[RBB]

How are i & j declared?

 

[magesh87ece]

Re: WHY?

how many input's temp reg has?


for loop will be executed in single clock cycle..............

 

[tkbits]

always without sensitivity list is a forever loop?