need help to modify 8*8 bit register

register

Hey people out there,

can someone please help me to modify how to make it 8*8 bit register. thank you

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
port(
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : out std_logic_vector(7 downto 0);
op: in std_logic_vector(2 downto 0)
);
END alu8bit;

architecture behavioral of alu8bit is
signal zero: std_logic;

begin

process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" => temp := a and b;
when "100" => temp := a and b;
when "001" => temp := a or b;
when "101" => temp := a or b;
when "010" => temp := a + b;
when "110" => temp := a - b;
when "111" => if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others => temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;


end behavioral;

Re: register

hi
you should first define a type then define a signal according your type.

type my_arr is array ((2**3) - 1 downto 0) of std_logic_vector (7 downto 0);
signal reg_8_8 : my_arr :=(others => (others => '0'));