madusnk said:
/.../i m not familiar with ise, qu(at)rtus/.../
if it's a university project I suspect there are 'school preferences'
about synthesis program and fpga then follow them - it'll be easier
to find advice/experts/hardware and to share experience;
if you have free choice @ltera software is slightly more user-friendly;
do not follow the recommendation [sorry Black Jack
]
to start with schematic entry, being familiar with the tool itself
you need no more then a week of exercises to write pretty useful
codes in verilog;
or you just need to complete this one school project and then forget
fpga staff forever - then schematics can be a good choice;