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Need Help on VHDL to write a Finite State Machine

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lahrach

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Hi friends,

I need to write a FSM that do this work:
Send N bits and receive the N bits then compare the N bits sended and the N bits received

best regards,
 

pseudo code:

state1: send N bits
state2: receive N bits
state3: compare bits

done.
 

my answer is almost the same with ads_ee's, but add another initial state, state 0, to reset all signals. and after all process is done, the FSM returns to the initial state 0.
 

yeah I considered adding that state, but thought that might give away too much, considering how the OP wants us to write the FSM for him, instead of asking how to fix his broken implementation after trying to make it work on his own (perhaps even learning something on the way). ;-)
 

yeah I considered adding that state, but thought that might give away too much, considering how the OP wants us to write the FSM for him, instead of asking how to fix his broken implementation after trying to make it work on his own (perhaps even learning something on the way). ;-)

Doesn't this just drive you crazy? It's just amazing how people continually post: "This is hard, I can't be bothered trying to do this. Can you do my homework for me?".
 

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