Need Help on combining two processes in VHDL

[Digit0001]

Hi

Can someone suggest how would i combine the following code into one process? The code is made up of a counter and a state machine which i want to make as one process. The problem i am having at the moment is the count will not work because it conflicts, hence i want to make it in one process.

architecture Behavioural of pulseDesign is
type StateType is (LowState,HighState);
signal nextState,state : StateType;
signal count : std_logic_vector(3 downto 0);

begin
---------------------------------------------
--Counter
	process(clk,reset,count)
	begin
		if(rising_edge(clk)) then
			State <= nextState;
			if(reset='1') then
				count <= "0000";
				State <= LowState;
			else
				count <= count + '1';
			end if;
		end if; 
         end process;
---------------------------------------------
--StateMachine
	process(state,pulse)
	begin
		temp <= "0000";
		case state is
			  when LowState =>
					if(pulse = '1') then
						temp <= count;
						count <= "0000";
						nextState <= LowState;
					else
						count <= count + 1;
						nextState <= HighState;
					end if;
				when HighState =>
					if(pulse = '1') then
						count <= count + 1;
						nextState <= HighState;
					else
						count <= count + 1;
						nextState <= LowState;
					end if;
		 end case;
	end process;
end Behavioural;

P.S

 

[TrickyDicky]

Think about what you are doing. The conflicts only occur because you're trying to assign count from 2 different places. You need to think about the logic.
You cannot have count in the asynchronous process because it is just that - asynchrnous.

basically, for a single process state machine:

process(clk, reset)  --only clock and reset needed in sensitivty list
begin
  if reset = '1' then
    count <= 0;
    state <= state0;
  elsif rising_edge(clk) then

    case state is
      when state0 => 
        count <= count + 1;
        state <= state1;

      when state1 => 
        --etc

 

[N vijay kumar]

hi,

begin
always@(posedge clk)
begin
if(reset)
count<=4'b0000;
presentstate<=LOW;
else
presentstate<=nextstate;
count<=cnt;
end

always@(presentstate,count)
begin
case presentstate
begin
LOW:
begin
cnt=4'b0000;
nextstate=HIGH;
end
HIGH:
begin
if(cnt=limit)
begin
nextstate=LOW;
cnt=4'b0000;
end//if begin
else
begin
nextstate=HIGH;
cnt=count+1;
end//else begin
end//state high begin
end//case begin
end//always begin
end //module begin

---------- Post added at 15:58 ---------- Previous post was at 15:56 ----------

i thin we can write like this.........

 

[TrickyDicky]

You posted Verilog in a thread about VHDL!

 

[Digit0001]

thanks, i understand now

 

[Digit0001]

i have a problem when i simulate the code. The modified code does not change states and the counter does not count. This is the code i have:
View attachment p_files.txt

this includes what i have in simulator and implementation.

 

[N vijay kumar]

dont mension state in sensitivity list

when LowState =>
temp <= "0000";
if(pulse = '1') then
temp <= count;//i dont under stud wy u used this temp regisrter
count <= "0000";// when pulse is present then counter to be counted => count=> count+1;
state <= LowState;//state=> HIGH;
else
count <= count + 1;//when no pulse count=> count;
state <= HighState;//state=> state;
end if;

when HighState =>
if(pulse = '1') then
count <= count + 1;
state <= HighState;
else
count <= count + 1;//when no pulse count=>count;
state <= LowState;//state=>state;
end if;

and when you r applying the signals to your code

-->apply reset first
-->apply signals at the neg edge of the clock

 

[Digit0001]

The temp is used to save the last count value. The purpose is because i am measuring the period of the pulse width.