architecture Behavioural of pulseDesign is
type StateType is (LowState,HighState);
signal nextState,state : StateType;
signal count : std_logic_vector(3 downto 0);
begin
---------------------------------------------
--Counter
process(clk,reset,count)
begin
if(rising_edge(clk)) then
State <= nextState;
if(reset='1') then
count <= "0000";
State <= LowState;
else
count <= count + '1';
end if;
end if;
end process;
---------------------------------------------
--StateMachine
process(state,pulse)
begin
temp <= "0000";
case state is
when LowState =>
if(pulse = '1') then
temp <= count;
count <= "0000";
nextState <= LowState;
else
count <= count + 1;
nextState <= HighState;
end if;
when HighState =>
if(pulse = '1') then
count <= count + 1;
nextState <= HighState;
else
count <= count + 1;
nextState <= LowState;
end if;
end case;
end process;
end Behavioural;