Need help in writing a tcl script to find out cells in the clock path

[pavan.mk]

Hello everyone,

Can anyone tell me how to find out the cells in the clock path? I am trying to write a tcl script to find out the cells in the clock path.

Thanks in advance

 

[iwpia50s]

When asking a question like this it helps to know the tool you are using because each tool has its own way of tagging cells.

 

[pavan.mk]

I am using RTL Compiler.

 

[sam536]

Did clock tree built when you are using RTLC?.

If you have PT licenese, its simple command.
get_clock_network_objects <> ; There might be equivalent command in RTLC or EDI. Jst check.

one more command to if you have more clocks in the design.

all_fanout -from -clock_tree ;which should have equivalent command in RTLC. Most of the PT comamnds support in RTLC, need to find out equivalent command.

Regards,
Sam

 

[pavan.mk]

Thanks sam536
Do you have any idea about other end arrival time? This I came across when I was analyzing a timing report.

 

[sam536]

Pavan,
Terminology depends on tools . Arrival times reffered in the PT reffered as Data arrival time from Launch Registers CLK pin to capture Register D pin( Including the clock n/w delay).

Regards, Sam

 

[pavan.mk]

In this example ,
Other End Arrival Time 3.278
- Setup 0.470
+ Phase Shift 25.000
+ CPPR Adjustment 0.000
= Required Time 27.808
- Arrival Time 26.292
= Slack Time 1.516

I see that there are two arrival time values. They both represent the time from the launch registers CLK pin to capature register D pin?

 

[sam536]

In this example, Other end arrival time is for Capture registers, where as arrival time is for Launch register. The launch register arrival time include the clock N/W delay.

Write the schematic for all the abobe timing path and write down the values seen in this.
you will be clear regarding all these things.

Regards, Sam

 

[tariq786]

There is one command in design compiler and primetime

all_registers

that will get you all the registers.Based on this execute the following tcl script. The idea is that you want to get registers and the associated clock port. If you have these two pieces of information together, then the problem is essentially solved.


# Tcl procedure to report the fan-in statistics of output ports or instance input pins
# Arguments:
# label user-specified string to designate the fanout type in the report file
# pin_name pin or input port to report statistics for
# module_scope current reporting scope
# report_file the name of the file to write statistics to


proc report_pin_fanin { label pin_name module_scope report_file } {
# Is pin_name an input port or cell pin?
set isport 0
if {[regexp {\.} $pin_name]} {
# this is a cell pin
set pin [get_pins $pin_name]
} else {
# this is a module port
set pin [get_ports $pin_name]
set isport 1
}
set startpoints [all_fanin -flat -startpoints_only -to $pin]
set startpoint_count [sizeof_collection $endpoints]
set logic_cone_pins [all_fanin -flat -to $pin]
set logic_cone_size [sizeof_collection $logic_cone_pins]
set reverse_traces_count na
# If we're reporting for a port, do the reverse lookup to see
# what else fans into the endpoints (used for fan-out-of-one check)
if {$isport} {
set reverse_traces_count 0
foreach_in_collection startpoint $startpoints {
set reverse_traces [all_fanout -flat -endpoints_only -to $startpoint]
incr reverse_traces_count [sizeof_collection $reverse_traces]
}
}
echo "$label $pin_name $module_scope $startpoint_count $logic_cone_size \
$reverse_traces_count" >> $report_file
}


### read verilog file from which to extract registers
read_verilog aes_cipher_top_syn.v
set module_scope aes_cipher_top_syn
set report_file "reg.rep"


foreach_in_collection reg [all_registers -cells -edge_triggered] {
set reg_full_name [get_object_name $reg]
# Report fanin stats for each register "D" pin
foreach_in_collection reg_pin [get_pins $reg_full_name/* -filter {pin_direction == in}] {
set reg_pin_name [get_object_name $reg_pin]
# only report for name ending with '.D' or 'next_state'
if {[regexp -nocase {\.D$|\/next_state} $reg_pin_name]} {
query_object $reg_pin_name
report_pin_fanin "ri" $reg_pin_name $module_scope $report_file
}
}
}