need help in ring oscillator transcient analysis

[kkantham]

ring oscillator

hi guys i have a problem in transcient analysis of 3 stage simple ring oscillator in 45nm cmos technology. i got dc analysis but with 3rd inverter in saturation.

i could not get transcient curves and could not measure delay parameters. this is my netlist can any body help me in correcting this

netlist
------------------------------------------------------------------
.option ingold
.param vdd=1.1
.ic v(1)=vdd

***********************************************************************
* Subcircuits
***********************************************************************

.subckt inv a y vdd 0 n=90n p=180n
M1 y a 0 0 nmos l=45n w='n' ad='0.5u*n' as='0.5u*n' pd='1u+2*n' ps='1u+2*n'
M2 y a vdd vdd pmos l=45n w='p' ad='0.5u*p' as='0.5u*p' pd='1u+2*p' ps='1u+2*p'

.ends inv


***********************************************************************
* Simulation netlist
***********************************************************************
vdd vdd 0 dc 'vdd'
vin 1 0 dc
x1 1 2 vdd 0 inv
x2 2 3 vdd 0 inv
x3 3 1 vdd 0 inv

.dc vin 0 'vdd' 0.05
.plot dc v(1) v(2) v(3)
.print dc v(1) v(2) v(3)




.tran .1ns 10ns
.plot tran v(1) v(2) v(3)
.measure tran tpdr TRIG v(2) val='vdd/2' fall=1 TARG v(3) val='vdd/2' rise=1
.measure tran tpdf TRIG v(2) val='vdd/2' rise=1 TARG v(3) val='vdd/2' fall=1
.measure tpd param='(tpdr+tpdf)/2'



.OP
.probe

**library input files**
.include `45nm.inc`
.end

can any body please help me in correcting this netlist to prevent saturation and to oscilllate to get curves in .tran analysis

 

[dick_freebird]

ring oscillator netlist

Your "vin" source is shunting the ring oscillator. Why?

 

[kkantham]

transcient

my professor told not to give any extrnal source/pulse to ring oscillator. so i left vin and gave .ic v(1)= vdd to start oscillation. but the last inverter in the loop went to saturation

 

[oermens]

ring oscillator anallysis

why don't you put IC on a small capacitor (you can even set it to 0F) connected to the output node instead? or put IC on the output net itself?

 

[dick_freebird]

ring oscillator tpd

Still that source is a zero AC impedance and ought to
bugger your transient runs.

If you want to kick something, a current source with a
zero value except at kick-time is better because it will
not interfere with anything. A small "supply noise"
voltage source is also possibly useful and fairly benign.

A ramped supply is somewhat credible although you
would need to bound the max risetime range for a real
part.

There is a very good chance your professor's instructions
will lead you to a circuit that doesn't start. Maybe that is
the lesson.

 

[oermens]

m1 0 in out 0 nmos l=90n w=120n

to summarize whats been mentioned, which are the usual ways of starting up an oscillator:

1. small cap on the output node with an initial condition, say 1nV
2. initial condition on the output net itself
3. ramp up the supply voltage
4. exponentially decaying sinusoidal current source

in any case, you can't put ic on a voltage/current source, you are just setting the value of that source. to put a source v=vdd at the output node means that the output node's value will always be vdd. although that '1' propagates to the input of the last stage, the output node is being forced to '1' by the voltage source so there is no oscillation.

 

[kkantham]

thank u my friends

what u said is true i tried to do it without source by adding inital condition v(1)=vdd. but as u said the node is always being forced to be vdd . so i removed the IC and added a pulse to initial node and it worked finally. however i got a very sharp curve in dc analysis such that i could'nt see the curve . what changes should i made to parameters to obtain smooth dc curve?

** 5-inverter: dc analysis**
.option ingold
.param vdd=1.1


***********************************************************************
* Subcircuits
***********************************************************************

.subckt inv a y vdd 0
M1 y a 0 0 nmos l=45n w=120n ad='1u*120n' as='1u*120n' pd='2u+240n' ps='2u+240n'
M2 y a vdd vdd pmos l=45n w=240n ad='1u*240n' as='1u*240n' pd='2u+480n' ps='2u+480n'
.ends inv


***********************************************************************
* Simulation netlist
***********************************************************************
vdd vdd 0 dc 'vdd'
vin 1 0 dc pulse( 0 'vdd' 5n 3n 3n 7n 13n)
x1 1 2 vdd 0 inv
x2 2 3 vdd 0 inv
x3 3 4 vdd 0 inv
x4 4 5 vdd 0 inv
x5 5 1 vdd 0 inv

.dc vin 0 'vdd' 0.05
.plot dc v(3) v(4) v(5)
.print dc v(3) v(4) v(5)


.tran 1ns 70ns
.plot tran v(3) v(4) v(5)

.measure tpdr TRIG v(3) val='vdd/2' fall=1 TARG v(4) val='vdd/2' rise=1
.measure tpdf TRIG v(3) val='vdd/2' rise=1 TARG v(4) val='vdd/2' fall=1
.measure tpd param='(tpdr+tpdf)/2'


*measurement of power -delay product*
.print p(vdd)
.measure pwr AVG p(vdd) FROM=0ns TO=70ns
.measure pdp param='(pwr*tpd)'
.plot tran p(vdd)*tpd
.plot dc p(vdd)*tpd



.OP
.probe

**library input files**
.include `45nm.inc`
.end

 

[oermens]

initial condtions using sources can cause more problems than using a passive component such as a small capacitor with initial voltage. in spectre i can add initial condition to a net:

ic Q\+=1n

this is from the netlist of a quad oscillator. maybe hspice is similar?

Added after 10 minutes:

example netlist:

// Library name: lab2
// Cell name: inv
// View name: schematic
subckt inv IN OUT
parameters Wp=1u Lp=180n Wn=1u Ln=180n
M1 (OUT IN vdd! vdd!) pch w=Wp l=Lp as=0.48u*(Wp) ad=0.48u*(Wp) \
ps=0.96u+2*(Wp) pd=0.96u+2*(Wp) nrd=0.27u/(Wp) nrs=0.27u/(Wp) m=1 \
region=triode
M0 (OUT IN 0 0) nch w=Wn l=Ln as=0.48u*(Wn) ad=0.48u*(Wn) \
ps=0.96u+2*(Wn) pd=0.96u+2*(Wn) nrd=0.27u/(Wn) nrs=0.27u/(Wn) m=1 \
region=triode
ends inv
// End of subcircuit definition.

// Library name: lab2
// Cell name: ringosc
// View name: schematic
C0 (net11 0) capacitor c=1a ic=1
V1 (vdd! 0) vsource dc=1.8 type=dc
V0 (0 0) vsource type=dc
I2 (net10 net11) inv Wp=1u Lp=180n Wn=1u Ln=180n
I1 (net12 net10) inv Wp=1u Lp=180n Wn=1u Ln=180n
I0 (net11 net12) inv Wp=1u Lp=180n Wn=1u Ln=180n